康佳LED46IS95D液晶电视35015699板（MST6I78ZX机芯）电路原理图

分类：电子电工日期：2023-03-27 点击：0

康佳LED46IS95D液晶电视35015699板（MST6I78ZX机芯）电路原理图-1

康佳LED46IS95D液晶电视35015699板（MST6I78ZX机芯）电路原理图-2

康佳LED46IS95D液晶电视35015699板（MST6I78ZX机芯）电路原理图-3

康佳LED46IS95D液晶电视35015699板（MST6I78ZX机芯）电路原理图-4

康佳LED46IS95D液晶电视35015699板（MST6I78ZX机芯）电路原理图-5

康佳LED46IS95D液晶电视35015699板（MST6I78ZX机芯）电路原理图-6

康佳LED46IS95D液晶电视35015699板（MST6I78ZX机芯）电路原理图-7

康佳LED46IS95D液晶电视35015699板（MST6I78ZX机芯）电路原理图-8

康佳LED46IS95D液晶电视35015699板（MST6I78ZX机芯）电路原理图-9

� � � � � � � � � � � � � � � � � � �� 05. DDR3_32Bit 6I78 988 Schematic Circuit Diagram 01. Cover Page 02. System Power 03. MST6I98_BGA_1 04. MST6I98_BGA_2 10. Tuner 08. AMP 07. YPbPr&AV 06. VGA 09. SubAMP 15. MEMC 13. Paraller flash 12. Ethernet 11. HDMI Interface 14. USB 16. TURN 17. Demod PAGE CONTENT Ver.xx 2010-10 PDF �� "PDF ��" �� http://www.fineprint.com � � � � � � � � � � � � � � � � � � �� 1.86V for MEMC DDR2 power 209mA 300mA DDR3 1.5V ��1.86V +3.3V NORMAL & MEMC VDD33 1.26V FOR 6i98 CORE POWER INPUT ��1.32V 160mA 6i98 2.5V 6i78 AU_3.3V +3.3V STANDBY POWER POWER_VCC3.3V_MEMC PANEL POWER 40mA DEMOD 2.5V 5VA DEMOD 1.2V 1.05V FOR 6M30 CORE �� + �� + �� + �� + �� + �� + �� + �� + �� + �� + �� + �� + �� + �� + �� + �� + �� + �� + �� + �� + �� + �� + �� + �� + �� + �� + �� + �� + �� + �� + �� + �� + �� + �� + �� + �� + �� + �� + �� + �� + �� + �� + �� PDF �� "PDF ��" �� NC �� 4'h0 4'h1 4'h2 4'h3 4'h4 4'h5 4'h6 4'h7 4'h8 4'h9 4'ha 4'hb 4'hc // CHIP Config {I2S_OUT_SD} Boot from SPI flash 1'b0 Boot from NOR flash 1'b1 {I2S_OUT_BCK, I2S_OUT_MCK, PAD_PWM1, PAD_PWM0} B51_no_EJ B51_EJ1 B51_EJ2 MIPS_no_EJ_NOR8 MIPS_EJ1_NOR8 MIPS_EJ2_NOR8 MIPS_no_EJ_NOR16 MIPS_EJ1_NOR16 MIPS_EJ2_NOR16 SBUS0 DBUS0 B51_Secure_no_scramble B51_Secure_scramble Mode Selection RESET POWER CUT DETECT GPIO PULL-UP EEPROM I2C address at A0 KEY I2C address at A8 VGA YPbPr1 LED_IR_KEY ADD for LAN ID AV3 SPI Flash Debug port �� AV1 �� NC FOR READY MAC I2C address at A4 Close to IC with width trace Close to chip I2C / UART JTAG MIPS E-JTAG #1 2010-5-19,��JTAT�� BOOT ROM ��4pin ��5pin �� LAN ID RTC EEPROM 120Hz�� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� AUDIO Line-In MIC-Phone Line-Out I2S-In I2S-Out SPDIF �� AUDIO Line-In MIC-Phone Line-Out I2S-In I2S-Out SPDIF �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� SAR PWM USB SPI Flash Crystal MI2C UART LVDS �� SAR PWM USB SPI Flash Crystal MI2C UART LVDS �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� 100BASE-TX Ethernet Parallel TS (IN) Front-End NAND FLASH Parallel TS (IN/OUT) PCMCIA �� 100BASE-TX Ethernet Parallel TS (IN) Front-End NAND FLASH Parallel TS (IN/OUT) PCMCIA �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� + �� + �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� PDF �� "PDF ��" �� DDR3 MIU0 Damping Resistors DDR3 MIU1 Damping Resistors �� DDR3 �� DDR3 �� HDMI RGB CVBS_IN S-Video CVBS_OUT �� HDMI RGB CVBS_IN S-Video CVBS_OUT �� Stand-by Power Normal Power �� Stand-by Power Normal Power �� PDF �� "PDF ��" �� B-MDATA4 �� A-MDATA9 A-MDATA3 �� A-MDATA15 �� A-MDATA1 �� B-MDATA10 �� B-MDATA2 �� B-MDATA0 B-MDATA14 A-MDATA10 �� A-MDATA6 �� B-MDATA12 �� A-MDATA2 �� B-MDATA8 �� A-MDATA14 �� A-MDATA0 A-MDATA12 �� B-MDATA6 A-MDATA8 A-MDATA4 �� For layout smooth DDR3_8Mx16x8Bank-FBGA96: Hynix_H5TQ1G63BFR-12C Nanya_NT5CB64M16AP-DG Elpida_EDJ1116DBSE-GN-F DDR3_8Mx16x8Bank-FBGA96: Hynix_H5TQ1G63BFR-12C Nanya_NT5CB64M16AP-DG Elpida_EDJ1116DBSE-GN-F 1st DDR3 Chip 2nd DDR3 Chip For layout smooth �� A B C D E F G H J K L M N P R 1 2 3 7 8 9 VDDQ DQU5 DQU7 VSSQ VDD VSS VDDQ DQU3 DQU1 VSSQ VDDQ DMU VSS VSSQ DQL0 VDDQ DQL2 DQSL VSSQ DQL6 DQSL# VREFDQ VDDQ DQL4 NC VSS RAS# VDD CAS# NC CS# WE# BA0 BA2 VDD A3 A0 A5 A2 VDD A7 A9 DQU4 VDDQ VSS DQSU# DQU6 VSSQ DQSU DQU2 VDDQ DQU0 VSSQ VDD DML VSSQ VDDQ DQL1 DQL3 VSSQ VDD VSS VSSQ DQL7 DQL5 VDDQ CK VSS NC CK# VDD CKE A10 ZQ NC VREFCA VSS A12 BA1 A1 A4 A11 A6 VSS ODT NC VSS VDD VSS VDD R VSS RST# NC NC A8 VSS �� A B C D E F G H J K L M N P R 1 2 3 7 8 9 VDDQ DQU5 DQU7 VSSQ VDD VSS VDDQ DQU3 DQU1 VSSQ VDDQ DMU VSS VSSQ DQL0 VDDQ DQL2 DQSL VSSQ DQL6 DQSL# VREFDQ VDDQ DQL4 NC VSS RAS# VDD CAS# NC CS# WE# BA0 BA2 VDD A3 A0 A5 A2 VDD A7 A9 DQU4 VDDQ VSS DQSU# DQU6 VSSQ DQSU DQU2 VDDQ DQU0 VSSQ VDD DML VSSQ VDDQ DQL1 DQL3 VSSQ VDD VSS VSSQ DQL7 DQL5 VDDQ CK VSS NC CK# VDD CKE A10 ZQ NC VREFCA VSS A12 BA1 A1 A4 A11 A6 VSS ODT NC VSS VDD VSS VDD R VSS RST# NC NC A8 VSS �� A B C D E F G H J K L M N P R 1 2 3 7 8 9 VDDQ DQU5 DQU7 VSSQ VDD VSS VDDQ DQU3 DQU1 VSSQ VDDQ DMU VSS VSSQ DQL0 VDDQ DQL2 DQSL VSSQ DQL6 DQSL# VREFDQ VDDQ DQL4 NC VSS RAS# VDD CAS# NC CS# WE# BA0 BA2 VDD A3 A0 A5 A2 VDD A7 A9 DQU4 VDDQ VSS DQSU# DQU6 VSSQ DQSU DQU2 VDDQ DQU0 VSSQ VDD DML VSSQ VDDQ DQL1 DQL3 VSSQ VDD VSS VSSQ DQL7 DQL5 VDDQ CK VSS NC CK# VDD CKE A10 ZQ NC VREFCA VSS A12 BA1 A1 A4 A11 A6 VSS ODT NC VSS VDD VSS VDD R VSS RST# NC NC A8 VSS �� A B C D E F G H J K L M N P R 1 2 3 7 8 9 VDDQ DQU5 DQU7 VSSQ VDD VSS VDDQ DQU3 DQU1 VSSQ VDDQ DMU VSS VSSQ DQL0 VDDQ DQL2 DQSL VSSQ DQL6 DQSL# VREFDQ VDDQ DQL4 NC VSS RAS# VDD CAS# NC CS# WE# BA0 BA2 VDD A3 A0 A5 A2 VDD A7 A9 DQU4 VDDQ VSS DQSU# DQU6 VSSQ DQSU DQU2 VDDQ DQU0 VSSQ VDD DML VSSQ VDDQ DQL1 DQL3 VSSQ VDD VSS VSSQ DQL7 DQL5 VDDQ CK VSS NC CK# VDD CKE A10 ZQ NC VREFCA VSS A12 BA1 A1 A4 A11 A6 VSS ODT NC VSS VDD VSS VDD R VSS RST# NC NC A8 VSS �� PDF �� "PDF ��" �� 2010-5-19,��VGA��N600/24C02 � � � �� PDF �� "PDF ��" �� Note:Close to MST. IC Keep A_GND trace with Signal. Keep Spacing for L/R cahnnel. Keep trace width(12mil+). �� 1.2VDC �� V602-E=1.2VDC ESD EPHONE OUT AV2/YPbPr AV3 IN Audio IN AV1 IN & SPDIF OUT VIDEO OUT AV OUT VGA_AUDIO_IN SPDIF OUT AV1 1. 12V�� 2. 5V�� R643 499�� R644 49.9�� R648 6.8K�� PDF �� "PDF ��" �� Mic_Drive AMP&HP OP AV_OUT Audio Out MUTE Control �� +L -L amplifier ON H 2.5~5V amplifier OFF L 0~0.5V MUTE Control Mute off H 2.5~5V Mute on L 0~0.5V +R -R STB CONTROL + �� + �� + �� + �� - + �� - + �� R2A15120FA �� R2A15120FA �� + �� + �� - + �� - + �� - + �� - + �� - + �� - + �� + �� + �� - + �� - + �� - + �� - + �� PDF �� "PDF ��" �� SAMP �� +L -L amplifier ON H 2.5~5V amplifier OFF L 0~0.5V MUTE Control Mute off H 2.5~5V Mute on L 0~0.5V +R -R STB CONTROL �� R2A15120FA �� R2A15120FA � � � � � - + �� - + �� - + �� - + �� + �� + �� - + �� - + �� PDF �� "PDF ��" �� RC�� Coil values will be updated W918 Close to pin 37 ��TV�� SAS��tuner�� 00——0~0.5V� 01——��1~1.5V� 10——2~3V� 11——4.5~5V� IIC LEVEL SHIFT TUNER POWER �� + �� + �� ±�� ±�� ±�� ±�� + �� + �� + �� + �� + �� + �� ±�� ±�� ±�� ±�� PDF �� "PDF ��" �� To MST IC For CEC Leakage Protect SIDE HDMI 2nd HDMI 1st HDMI �� Hot-Plug Control �� PDF �� "PDF ��" �� 50MHz CLOCK OUT Generate by IP101A Set IP101A to RMII Mode �� BANDGAP RESISTOR Pin48 could be short VDD33 if interrupt funtion is not used. As close to IP101A Pin14 as possible As close to IP101A Pin36 as possible CRYSTAL as close as to chip LED and PHY address Configuration This schematic sets PHY address to 00001b. LED0 LED1 LED2 LED3 LED4 Link Dupx 10Act 100Act COL As close to IP101A Pin32 as possible As close to IP101A Pin8 as possible * : Optional ,but recommended ** Bead should be placed as close to IP101A as possible and in the same side as IP101A. Y G 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� RJ-45 - + + - �� RJ-45 - + + - �� PDF �� "PDF ��" �� PDF �� "PDF ��" �� +5V USB from 5Vstb �� Active Hub Indicator Not required �� +5V USB from 12V �� + �� + �� + �� + �� + �� + �� 4 3 2 1 �� 4 3 2 1 �� 4 3 2 1 �� 4 3 2 1 �� + �� + �� + �� + �� 4 3 2 1 �� 4 3 2 1 �� + �� + �� PDF �� "PDF ��" �� Close to MST IC VSS ��AP1702�� Place Close to DRAM LVDS IN For Local dimming function, use 1M bit(128K byte)SPI flash VSS VSS GPIO1: two chip use H: Master L: Slave CHIP_CONF: {GPIO8, PWM1, PWM0} CHIP_CONF= 3ˇd5: 101 : boot from internal SRAM CHIP_CONF= 3ˇd6: 110 : boot from EEPROM CHIP_CONF= 3ˇd7: 111 : boot from SPI Flash RESET DDR2 : 1066Mbps,512Mbit VDDC VDDP �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� 3 1 4 2 �� 3 1 4 2 �� + �� + �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� + �� + �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� A B C D E F G H J K L M N P R 1 2 3 7 8 9 Vdd NC Vss DQ14 VssQ UDM VddQ DQ9 VddQ DQ12 VssQ DQ11 Vdd NC Vss DQ6 VssQ LDM VddQ DQ1 VddQ DQ4 VssQ DQ3 VddL Vref Vss CKE WE# RFU BA0 BA1 A10 A1 Vss A3 A5 A7 A9 Vdd A12 RFU VssQ UDQS# VddQ UDQS VssQ DQ15 VddQ DQ8 VddQ DQ10 VssQ DQ13 VssQ LDQS# VddQ LDQS VssQ DQ7 VddQ DQ0 VddQ DQ2 VssQ DQ5 VssDL CK Vdd RAS# CK# ODT CAS# CS# A2 A0 Vdd A6 A4 A11 A8 RFU NC Vss �� A B C D E F G H J K L M N P R 1 2 3 7 8 9 Vdd NC Vss DQ14 VssQ UDM VddQ DQ9 VddQ DQ12 VssQ DQ11 Vdd NC Vss DQ6 VssQ LDM VddQ DQ1 VddQ DQ4 VssQ DQ3 VddL Vref Vss CKE WE# RFU BA0 BA1 A10 A1 Vss A3 A5 A7 A9 Vdd A12 RFU VssQ UDQS# VddQ UDQS VssQ DQ15 VddQ DQ8 VddQ DQ10 VssQ DQ13 VssQ LDQS# VddQ LDQS VssQ DQ7 VddQ DQ0 VddQ DQ2 VssQ DQ5 VssDL CK Vdd RAS# CK# ODT CAS# CS# A2 A0 Vdd A6 A4 A11 A8 RFU NC Vss �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� MST6M30SL 2-CH LVDS in / 4-CH LVDS out DDR2-16 �� MST6M30SL 2-CH LVDS in / 4-CH LVDS out DDR2-16 �� + �� + �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� 3 1 4 2 �� 3 1 4 2 �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� 3 1 4 2 �� 3 1 4 2 �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� 3 1 4 2 �� 3 1 4 2 �� PDF �� "PDF ��" �� 3D_5V �� 400mA MAX �� 3V3�� 25003822 +2��D1250-02AD(90° SMT)/R �� + �� + �� PDF �� "PDF ��" �� AAGND AAGND �� AAGND AAGNDAAGND VDD2.5 VDD1.2 VDD1.2 VDD2.5 �� VDD2.5 VDD1.2 VDD2.5 VDD2.5 VDD1.2 VDD2.5 VDD1.2 DEMO_3V3 VDD2.5 VDD1.2 VDD2.5 VDD2.5 VDD2.5 VDD2.5 VDD1.2 VDD1.2 VDD2.5 VDD1.2 VDD1.2 VDD2.5 VDD2.5 VDD2.5 VDD2.5 VDD2.5 VDD1.2 AAGND �� LOCK 10uF Caps for VDD1.2 Power Plane to Dig GND Cap at each VDD2.5 pin of N107 equal to or greater than 500uS From reset circuit active low VBIAS (nominally 1.5V) Cap placed at each VDD1.2 pin of N107 Bypassing for 8G75 If Sleep Mode function is required, control of this pin will be from an external source. This pin has a 10K pullup resistor internal to the package. J6 = N/C (open), demod normal operating mode J6 = logic 1, demod normal operating mode J6 = Logic 0, demod in sleep mode TO THE TUNER 2.5V 0V TO THE MPEG DECODER 2.5V/ 200mA / 1.2V / 800mA ERROR 144 Pin BGA w/ R15 = NU I2C Address = 3A w/ R15 = 10K I2C Address = 32 DEMO AGC Switch AGC SWITCH 8296 AGC Switch �� + �� + �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� + �� + �� 7 5 3 1 8 6 4 2 �� 7 5 3 1 8 6 4 2 �� PDF �� "PDF ��" ��

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康佳LED46IS95D液晶电视35015699板（MST6I78ZX机芯）电路原理图

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