索尼SONY DP-IF8000音响电路图
US Model
Canadian Model
AEP Model
SERVICE MANUAL
DIGITAL SURROUND PROCESSOR
SPECIFICATIONS
DP-IF8000
Ver 1.0 2002.02
Sony Corporation
Parsonal Audio Company
Published by Sony Engineering Corporation
9-873-528-01
2002B0200-1
© 2002. 02
•
Manufactured under license from Dolby Laboratories and Digital
Theater Systems,Inc.
“Dolby ”,“AC-3 ”,“Pro Logic ”,the “AAC ” logo and the double-D
symbol ; are trademarks of Dolby Laboratories.
“DTS ” and “DTS VIRTUAL ” are trademarks of Digital Theater
Systems, Inc.
•
DP-IF8000 is the component model block one in
MDR-DS8000.
COMPONENT MODEL NAME FOR MDR-DS8000
DIGITAL SURROUND PROCESSOR
DP-IF8000
CORDLESS STEREO HEADPHONES
MDR-IF8000
Decoder functions
Dolby Digital
Dolby Pro Logic II
DTS
DTS-ES 6.1ch
MPEG-2 AAC
Virtual sound function
OFF
Virtual front
Virtual surround 5.1 & 6.1
Modulation System
DQPSK
Secondary carrier wave frequency
4.5 MHz
Transmission distance
Approx. 10 m to the front
Transmission range
12 – 24,000 Hz
Distortion rate
1% or less (1 kHz)
Audio inputs
Optical input
(rectangular-type) × 2
Analogue input
(pin jack left/right) × 1
Power requirements
DC 9 V (from the supplied AC
power adaptor)
Dimensions (w/h/d)
Approx. 85 × 190 × 200mm (3 3 /8×
7 1 /2 × 7 1 /8 inch)
Mass
Approx.1.0 kg(2 lb 30 oz)
Design and specifications are subject to change without notice.
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DP-IF8000
SAFETY-RELATED COMPONENT WARNING!!
COMPONENTS IDENTIFIED BY MARK 0 OR DOTTED LINE WITH
MARK 0 ON THE SCHEMATIC DIAGRAMS AND IN THE PARTS
LIST ARE CRITICAL TO SAFE OPERATION. REPLACE THESE
COMPONENTS WITH SONY PARTS WHOSE PART NUMBERS AP-
PEAR AS SHOWN IN THIS MANUAL OR IN SUPPLEMENTS PUB-
LISHED BY SONY.
ATTENTION AU COMPOSANT AYANT RAPPORT
À LA SÉCURITÉ!
LES COMPOSANTS IDENTIFÉS PAR UNE MARQUE 0 SUR LES
DIAGRAMMES SCHÉMATIQUES ET LA LISTE DES PIÈCES SONT
CRITIQUES POUR LA SÉCURITÉ DE FONCTIONNEMENT. NE
REMPLACER CES COMPOSANTS QUE PAR DES PIÈSES SONY
DONT LES NUMÉROS SONT DONNÉS DANS CE MANUEL OU
DANS LES SUPPÉMENTS PUBLIÉS PAR SONY.
Notes on chip component replacement
• Never reuse a disconnected chip component.
• Notice that the minus side of a tantalum capacitor may be
damaged by heat.
Flexible Circuit Board Repairing
• Keep the temperature of soldering iron around 270˚C during
repairing.
• Do not touch the soldering iron on the same conductor of the
circuit board (within 3 times).
• Be careful not to apply force on the conductor when soldering
or unsoldering.
Flexible Circuit Board Repairing
TABLE OF CONTENTS
1. GENERAL .......................................................................... 2
2. SERVICING NOTES ........................................................ 3
3. DISASSEMBLY
3-1. Cover ................................................................................... 9
3-2. Chassis (processor), "Panel ASSY, Front" .......................... 9
3-3. TX Board .......................................................................... 10
3-4. LED Board, AMP Board ................................................... 10
4. TEST MODE ......................................................................11
5. ELCTORICAL AJUSTMENT.........................................12
6. DIAGRAMS
6-1. Explanation of IC Terminal ............................................... 13
6-2. Block Diagram (1/2) – ....................................................... 18
6-3. Block Diagram (2/2) – ....................................................... 19
6-4. Printing Wirning Board – LED Section – .......................... 20
6-5. Schematic Diagram – LED Section – ................................ 21
6-6. Printed Wiring Board – TX Section –................................ 22
6-7. Schematic Diagram – TX Section (1/4) –.......................... 23
6-8. Schematic Diagram – TX Section (2/4) –.......................... 24
6-9. Schematic Diagram – TX Section (3/4) –.......................... 25
6-10. Schematic Diagram – TX Section (4/4) – ......................... 26
7. EXPLODED VIEWS ........................................................ 29
8. ELECTRICAL PARTS LIST ........................................30
SECTION 1
GENERAL
This section is extracted from
instruction manual.
Front Panel of the
Processor
1 DIGITAL 1,2 input indicator
ANALOG input indicator
INPUT button
Press to select the input source (DIGITAL
1/DIGITAL 2/ANALOG).
2 POWER indicator
This indicator lights green when you
turn on the processor.
POWER switch
Press to turn on and off the processor.
3 CINEMA 1,2 indicator
MUSIC indicator
EFFECT button (see page 20 for
details)
Press to select the sound field (CINEMA
1/CINEMA 2/MUSIC).
4 Decode mode indicator (see page
19 for details)
5 PHONES jack (see page 20, 24 for
details)
Connect your headphones to this jack.
Connect the MDR-F1 headphone (sold
separately) for optimum surround effect.
6 PHONES — LEVEL control
Turn to adjust the volume of the
headphones (sold separately) connected
to the PHONES jack.
7 OUTPUT button
Press to select the output mode (OFF/
VIRTUAL FRONT/VIRTUAL
SURROUND).
8 Infrared emitter
Set the emitter in a position so that there
is a straight, unobstructed path to the
sensor.
PHONES
LEVEL
MIN
MAX
VIRTUAL
OUTPUT
L
POWER
DIGITAL 2
ANALOG
DIGITAL 1
INPUT
CINEMA 1
CINEMA 2
MUSIC
EFFECT
DECODE MODE
DOLBY DIGITAL
DOLBY PRO LOGIC II
DTS
C
R
LS
RS
CS
MPEG-2 AAC
1
6
7
8
5
1
2
3
Rear Panel of the
Processor
1 DIGITAL IN 1,2 jack (see page 13 for
details)
Connect a DVD player, Digital TV,
Digital Broadcasting Satellite Receiver,
LD player, or other digital component
(sold separately) to this jack.
2 ATT (attenuator) switch
Set this switch to 0dB when the volume is
too low at analogue input. Normally, this
switch should be set to –8dB.
3 LINE IN jack (see page 14 for details)
Connect the audio output jack on audio/
video equipment (sold separately), such
as a video cassette player or TV, to this
jack.
4 DC IN jack
Connect the supplied AC power adaptor
to this jack. (Be sure to use the supplied
AC power adaptor. Using products with
different plug polarity or other
characteristics can cause a malfunction.)
1
2
3
4
LOCATING THE CONTROLS
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DP-IF8000
SECTION 2
SERVICING NOTES
DIAT
(DIGITAL INFRARED AUDIO TRANSMISSION)
High quality media such as DVD and digital broadcasts are currently going through a phase of explosive expansion. To convey these kinds
of high quality media to listeners with no loss in sound nuance or quality, a new technology called DIAT has been developed using the MDR-
DS8000 to transmit these digital audio signals by infrared without harmful data compression.
DIAT technology allows transmitting digital audio signals without data compression on a portion of the sub-carrier frequency bandwidth
allotted to distributing high-fidelity audio by the IEC (International Electrotechnical Commission) and JEITA (Japan Electronic Information
Technical Association). The transmission quality is equal to or better than that on compact discs (CD). (Fig. 2-6)
L
2
3
4
6
Hi-Fi audio data transmission bandwidth
(2 to 6 MHz)
Analog transmission
Digital transmission (DIAT)
[MHz]
R
5
Fig. 2-6 Signal spectrum for digital infrared transmission
[Reference Data]
Sub-carrier frequency
: 4.5 MHz
Occupied bandwidth
: 2.5 MHz (approx.)
Data rate
: 3 Mbps (approx.)
Modulation method
: DQPSK
(differential quadrature phase shift keying)
Transmit error correction : Reed Solomon coding
DIGITAL INFRARED AUDIO TRANSMISSION
Along with developing a custom IC, the number of light-emitter elements were doubled (to 16) and light-receiver elements increased 6-fold
(to 24) to achieve a carrier-to-noise signal ratio well capable of transmitting wide-band digital signals. Using digital transmission eliminates
the transmission hiss noise heard in conventional analog broadcasts and allows listeners to enjoy hearing even small sounds.
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DP-IF8000
1. STATUS TRANSITION DRAWING
1.1
Processor
ALL POWER OFF
(LEDs all off)
TEST
MODE
POWER OFF
(LEDs all light up)
INPUT
CHANGE
OUTPUT
CHANGE
EFFECT
CHANGE
Unplug the AC adapter
POWER key
POWER key
Press EFFECT key
while in Virtual output
mode
INPUT key
OUTPUT key
After operation change
After operation change
After operation
change
OFF out put
(L-HLch, L-HRch lights up)
Virtual front output
(L-FLch, L-FRch, L-VIRTUAL
lights up)
5.1ch virtual output
(L-FLch, L-FCch, L-FRch
L-SLch, L-SRch, L-VIRTUAL
lights up)
6.1ch virtual output
(L-FLch, L-FCch, L-FRch
L-SLch, L-SCch, L-SRch,
L-VIRTUAL lights up)
CINEMA1 sound effect
(L-CINEMA1 lights up)
CINEMA2 sound effect
(L-CINEMA2 lights up)
MUSIC sound effect
(L-MUSIC lights up)
Digital input 1 enabled
(L-DIGITAL 1 lights up)
Digital input 2 enabled
(L-DIGITAL 2 lights up)
Analog input enabled
(L-ANALOG lights up)
Unplug the AC
adapter
Unplug the AC adapter
Connect the AC adapter
Connect AC adapter while simultaneously
pressing POWER & INPUT
POWER ON
(operation LED lights up)
1.2 Headphones
POWER OFF
(L-POWER off)
POWER ON
(L-POWER lights up)
EFFECT
CHANGE
EFFECT
CHANGE
• Virtual output (head trcking on)
• Virtual output (head trcking off)
LOW BATTERY
operation
Place headphones on head.
When LOW BATTERY
is detected
When virtual output (processor output)
is changed or S-HT changed while S-HT
is enabled.
Remove headphones
When switched to stereo-thru
output (processor output)
Receive error
operation
Processor infrared ray output to
OFF at transmit limit or cutoff.
After operation change
After operation change
Through output
(head tracking off)
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DP-IF8000
2. WAVEFORMS & TIMING OF MAIN SIGNAL LINES
2.1 Processor
2.1.1 Audio system
Note: Switch to Digital Input mode by connecting the optical cable
to DIGITAL IN 1 or 2, and pressing the INPUT key.
Switch to Analog Input mode by connecting the audio cable
to LINE IN, and pressing the INPUT key.
• Master clock
MCK (IC12-104pin) : 12.288 MHz (fixed)
MCKADDA (IC5-6pin) : 12.288 MHz (fixed) when in analog
input mode;
When in Digital Input mode, 12.288 MHz for an input source
sampling frequency of 48 kHz.
11.298 MHz for an input sampling frequency of 44.1 kHz; 8.192
MHz for an input sampling frequency of 32 kHz
• DIR-DECODER period
Check LRCK (IC11-12pin), BCK (IC 11-14pin), INDATA (IC11-
10pin).
At power-ON, and in Digital Input mode, any playback source is
okay.
Monitor view is shown in Fig. 1 and detailed timing is shown in
Fig. 2.
Fig 2
LRCK
BCK
INDATA
16 bit
1 bit offset (I2S format)
Fig1
LRCK
BCK
INDATA
Lch
Rch
Note 1: Example shows 44.1 kHz for LRCK; 48 kHz and
32 kHz are also used.
Fig 3
LRCK
BCK
INDATA
Lch
Rch
Note 2: LRCK is fixed at 48 kHz.
• ACD-DECODER period
Check LRCK (IC11-12pin), BCK(IC 11-14pin), INDATA (IC11-
10pin).
At power-ON, and in Digital Input mode, any playback source is
okay.
Monitor view is shown in Fig. 3 and detailed timing is shown in
Fig. 4.
Fig 4
LRCK
BCK
INDATA
24 bit
1 bit offset (I2S format)
Fig 5
LRCK
BCK
FLRSG
SLRSG
CLFSG
LFE
FLch
FRch
Note 3: Example shows 48 kHz for LRCK, but 44.1 kHz and
32 kHz may also be used.
• DECODER-MAIN DSP period
Check LRCK (IC11-12pin), BCK (IC 11-14pin), FLRSG (IC11-4pin),
SLRSG (IC11-5pin), CLFSG (IC11-6pin), OTHSG (IC11-7pin).
The playback source at power-ON, and Digital Input mode is Dolby
Digital or DTS, or a 5.1ch source for MPEG-AAC.
The view on the monitor when OFF or VIRTUAL FRONT is se-
lected with the OUTPUT key is shown in Fig. 5. The detailed timing
is shown in Fig. 6.
Fig 6
LRCK
BCK
FLRSG
SLRSG
CLFSG
1 bit offset (I
2S format)
Fig. 7 shows the monitor view when VIRTUAL 5.1 is selected with
the OUTPUT key. (Detailed timing is the same as in Fig. 6.)
Fig. 8 shows the monitor view when VIRTUAL 6.1 is selected with
the OUTPUT key. (Detailed timing is the same as in Fig. 6.)
Fig 7
LRCK
BCK
FLRSG
SLRSG
CLFSG
FL
FR
SL
SR
C
LFE
Note 3: Example shows 48 kHz for LRCK, 44.1 kHz and
32 kHz are also used.
Fig 8
LRCK
BCK
FLRSG
SLRSG
CLFSG
OTHSG
FL
FR
SL
CS
SR
C
LFE
Note 3: Example shows 48 kHz for LRCK, 44.1 kHz and
32 kHz are also used.
• MAIN DSP-DAC period
Check LRCK (IC5-5pin), BCK (IC5-4pin), VPOUT2 (IC15-3pin).
At power-ON, and Digital Input mode or Analog Input mode, any
playback source is okay.
A monitor view is shown in Fig. 9 and the detailed timing is shown
in Fig. 10.
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DP-IF8000
• MAIN DSP-DIAT period
Check RCS (IC12-109pin), BCK (IC12-106), VPOUT1 (IC12-
96pin), RINFO (IC12-107pin).
Turn the power on, set in Digital Input mode, and select VIRTUAL
FRONT, or VIRTUAL 5.1 or VIRTUAL 6.1 with the OUTPUT
switch.
The view on the monitor when the input source sampling frequency
is 48 kHz is shown in Fig. 11.
The view on the monitor when the input source sampling frequency
is 44.1 kHz is shown in Fig. 12.
The view on the monitor when the input source sampling frequency
is 32 kHz is shown in Fig. 13.
Fig 9
LRCK
BCK
LPOUT2
Lch
Rch
Note 3: Example shows 48 kHz for LRCK, 44.1 kHz and
32 kHz are also used.
Fig 10
LRCK
BCK
VPOUT2
Fig 11
RCS
BCK
VPOU1
RINFO
0001000 t fs=48k
Note 4: fs=48kHz
Fig 12
RCS
BCK
VPOU1
RINFO
0000000 t fs=44.1k
Note 5: fs=44.1kHz
Fig 13
RCS
BCK
VPOU1
RINFO
0011000 t fs=32k
Note 6: fs=32kHz
When OFF is selected with the OUTPUT key, check the DILRCK
(IC12-98pin), BCK (IC12-106pin), VPOUT1 (IC12-96pin), and the
view on the monitor should be the same as the MAIN DSP-DAC
period.
2.1.2
System Control
Note: Input a signal of some kind to DIGITAL IN 1 and LINE IN.
• MICON-DIR period
Check the DIR_XCS (IC4-37pin), SCK2 (IC4-38pin), and SDO2
(IC4-36pin).
Figure 14 shows the view on the monitor after power is turned on,
at the instant of switching with the INPUT key.
Fig 14
DIR_XCS
SCK
(500KHZ)
SDO2
Address
8 bit
00010111
data
8 bit + 8 bit
• MICON-DAC period
Check the DAC_XCS (IC5-10pin), SCKO (IC5-8pin), and SDO02
(IC5-9pin).
Figure 15 shows the view on the monitor after power is turned on,
at the instant of switching with the INPUT key.
Fig 15
DAC_XCS
SCK 0
(500KHZ)
SDO 0
Address
8 bit
00100000
data
8 bit + 8 bit
• MICON-LED DRIVER period
Check the LED_XLAT (CN102-3pin), SCKO(CN102-6pin), and
SDO(CN102-7pin).
Figure 16 shows the view on the monitor after power is turned on,
at the instant of switching with each key.
Fig 16
LED_XLAT
SCK 0
(500KHZ)
SDO 0
8 bit + 8 bit
after data transfer LAT
• MICON-DIAT period
Check the DIAT_LAT (IC12-152pin), SCKO (IC12-151pin), SDO
(IC12-153pin).
Figure 17 shows the view on the monitor after power is turned on,
at the instant of switching with the INPUT key. The timing is shown
in detail in FIG. 18.
Fig 17
DIAT_LAT
SCK 0
SDO 0
Fig 18
DIAT_LAT
SCK 0
(500KHZ)
SDO 0
after 24bit data transfer LAT
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DP-IF8000
• MICON-DECODER period
Check the DEC_XCS (IC11-2pin), SCK1 (IC11-1pin), SDO1 (IC11-
143pin), SDI1 (IC11-144pin).
Figure 19 shows the view on the monitor after power is turned on,
at the instant of switching with the OUTPUT key. The timing is
shown in detail in FIG. 20.
Fig 19
DEC_XCS
SCK 1
SDO 1
SDI 1
Sending the
24 bit data
Receiving the
24 bit data (example)
Fig 20
DEC_XCS
SCK 1
(1MHz)
SDO 1
SDI 1
• MICON-MAIN DSP period
Check the DSP_XCS (IC19-2pin), SCK1 (IC19-1pin), SDO1 (IC19-
143pin), and the DSP_XHREQ (IC19-3pin).
Figure 21 shows the view on the monitor after power is turned on,
at the instant of switching with the OUTPUT key. (The detailed
timing is the shown as shown in FIG. 20.
Fig 21
DSP_XCS
SCK 1
(1MHz)
SDO 1
DSP_XHREQ
Start of 24 bit data transfer, at 2nd bit, HREQ t 1
After transfer of 24 bit data, HREQ t 0
2.2 Headphones
2.2.1 Audio System
Note: Switch to Digital Input mode by connecting the optical cable
to DIGITAL IN 1 or 2, and pressing the INPUT key.
• Master clock
DSP_MCK(IC501-34pin) : 12.288 MHz (fixed)
DAC_MCK (IC102-2pin) : 12.288 MHz when the input source sam-
pling frequency to the processor is 48 kHz.
11.289 MHz when the sampling frequency is 44.1 kHz
8.192 MHz when the sampling frequency is 32 kHz
• DIAT-DSP period
Check the LRCK/RCS (IC501-94pin), BCK (IC501-6pin),
DIAT_OUT (IC501-20pin), RINFO (IC501-19pin).
Turn the power on, set in Digital Input mode, and select VIRTUAL
FRONT, or VIRTUAL 5.1 or VIRTUAL 6.1 with the OUTPUT
key.
Turn the headphone power on.
The view on the monitor when the input source sampling frequency
to the processor is 48 kHz is shown in Fig. 22.
The view on the monitor when the input source sampling frequency
to the processor is 44.1 kHz is shown in Fig. 23.
The view on the monitor when the input source sampling frequency
to the processor is 32 kHz is shown in Fig. 24.
The view on the monitor when OFF is selected with the OUTPUT
key is shown in Fig. 25. The detailed timing is shown in Fig. 26.
Fig 22
LRCK/RCS
BCK
DIAT_OUT
RINFO
0001000 t fs=48k
Note 7: fs=48kHz
Fig 23
LRCK/RCS
BCK
DIAT_OUT
RINFO
0000000 t fs=44.1k
Note 8: fs=44.1kHz
Fig 24
LRCK/RCS
BCK
DIAT_OUT
RINFO
0011000 t fs=32k
Note 9: fs=32kHz
Fig 25
Lch
Rch
LRCK/RCS
BCK
DIAT_OUT
RINFO
Note 10: Only LRCK, BCK and DATA are enabled. RINFO
is disabled.
Fig 26
LRCK/RCS
BCK
DIAT_OUT
RINFO
• DSP-DAC period
Check the LRCK (IC102-16pin), BCK (IC102-14pin), and
DSP_OUT (IC102-15pin).
Turn on the processor and set to Digital Input mode. Turn on the
headphone power, and apply an input source signal (any kind is
okay) to the processor.
The view on the monitor is shown in Fig. 27, and the detailed tim-
ing is shown in Fig. 28.
Fig 27
LRCK
BCK
DSP_OUT
Lch
Rch
Fig 28
LRCK
BCK
DSP_OUT
1 bit offset (I2S format)
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DP-IF8000
2.2.2 System Control
• MICON-DSP period
Check the DSP_XCS (IC501-23pin), SCK (IC501-26pin), SDO
(IC501-24pin), and XHREQ (IC501-27pin).
The view after turning on the headphone power is shown in Fig. 29,
and the detailed timing is shown in Fig. 30.
Fig 29
DSP_XCS
SCK
SDO
XHREQ
Fig 30
DSP_XCS
SCK
(625kHz)
SDO
XHREQ
Start of 24 bit data transfer, at 2nd bit, HREQ t 1
After transfer of 24 bit data, HREQ t 0
• DIAT-MICON-DSP period
Check the DTQ (IC901-28pin), DSP_DTQ (IC501-28pin), ARDET
(IC901-27pin), DIAT_DTSEL (IC101-16pin).
Turn on the processor and set to Digital Input mode. Turn on the
headphone power, and apply an input source signal (any kind is
okay) to the processor.
The instant when switching from OFF to VIRTUAL FRONT using
the processor OUTPUT key is shown in Fig. 31.
The monitor view at the instant when switching from VIRTUAL
FRONT to VIRTUAL 5.1 or from VIRTUAL 5.1 to VIRTUAL 6.1
with the processor OUTPUT key is shown in Fig. 32.
The monitor view at the instant when switching from VIRTUAL
5.1 or VIRTUAL 6.1 to OFF with the processor OUTPUT key is
shown in Fig. 33.
Fig 31
*1
DTQ
DSP_DTQ
ARDET
DIAT_DTSEL
Set DIAT receive
mode *3
Infrared unlock
(receive NG)
Infrared lock (receive OK)
Report lock to DPS
DSP identifies processor
transmit mode *2
*1 Pulse output when set to DIAT receive mode.
*2 ARDET = 1 t VIRTUAL mode
ARDET = 0 t OFF mode
*3 Approximately 25 msec from lock report to DSP until DIAT
receive mode is set.
DTSEL t VIRTUAL mode
DTSEL = 0 t OFF mode
Fig 32
DTQ
DSP_DTQ
ARDET
DIAT_DTSEL
Fig 33
DTQ
DSP_DTQ
ARDET
DIAT_DTSEL
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1
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9
DP-IF8000
SECTION 3
DISASSEMBLY
3-1. COVER
• This set can be disassembled in the order shown below.
Note: Follow the disassembly procedure in the numerical order given.
Set
Chassis (processor), “Panel ASSY, front”
TX board
LED board, AMP board
Cover
3 Two screws (+BVTT 2.6X5)
5 Cover
2 Two screws (+BVTT 2.6X5)
1 Two screws (+BVTT 2.6X5)
4 Two screws (+BVTT 2.6X5)
3-2. CHASSIS (PROCESSOR), “PANEL ASSY, FRONT”
4 Two screws (+P 3X8)
7 Screw (+P 3X8)
5 Two screws(+P)
8 Claw
Panel ASSY, front
3 CN102
2 CN002
6 Screw (+BTT)
Chassis (processor)
9
1 CN001
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DP-IF8000
3-4. LED BOARD, AMP BOARD
3-3. TX BOARD
Chassis (processor)
3 Two screws (+BTT)
2 Screw
1 Three screws (+P 3X8)
TX board
1 Two screws (+P 2X8)
Panel ASSY, front
2 Three screws (+P 2X8)
3 LED board
4 Screw (+P 2X8)
5 AMP board
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11
DP-IF8000
SECTION 4
TEST MODE
1. OVERVIEW
The internal microprocessor in this device has a test mode that can
perform all checks. Items that must be checked during repairs are
stored in this microprocessor.
2. SETTING THE TEST MODE
To call up test mode, turn on the power while holding down the
POWER and INPUT keys. (Connect the AC adapter.)
3. CANCEL THE TEST MODE
Remove the AC adapter.
4. TEST MODE
4-1. LED check
To Key check
LEDs light up in sequence *1)
*1) Test mode setup status
EFFECT key
EFFECT key
All LEDs light up *2)
*2) Infrared LEDs shall light up
All LEDs turn off *3)
*3) Infrared LEDs shall turn off
Power key
4-2. Key Check
*5) Decode mode LED
*4) Matching LED
POWER key : POWER LED, WINDOW LED
INPUT key : DIGITAL1, DIGITAL2,
ANAGOG LED
EFFECT key : CINEMA1, CINEMA2,
MUSIC LED
OUTPUT key : DECODE MODE LED
L
C
R
LS
VIRTUAL
CS
RS
HR LED
HL LED
Pressing the INPUT, EFFECT or
OUTPUT key lights up the matching
LED *4)
POWER key
To test tone output
5. TEST TONE OUTPUT
DIGITAL1
L, R, HL, HR
LED lights up
DIGITAL2
L, R, HL, HR
LED lights up
ANALOG
L, R, HL, HR
C LED lights up
CINEMA1
L, R, HL, HR
R LED lights up
INPUT key
INPUT key
INPUT key
EFFECT key
POWER key
1kHz, 0dBv L&R ch
*6)
1kHz, –10dBv L&R ch
*6)
100Hz, –10dBv L&R ch
*6)
10kHz, –10dBv L&R ch
*6)
End test mode
Shift to normal power-on operation
DIGITAL1
L, R, HR LED lights up
DIGITAL1
L, R LED lights up
DIGITAL1
HL, HR LED lights up
L&R ch output
L ch ouput
(R ch MUTE)
R ch output
(L ch MUTE)
*6) Pressing the OUTPUT key in each test mode changes
the output channels as shown below.
(e.g.) During L&R channel output at 1 kHz and 0dBv.
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12
DP-IF8000
SECTION 5
ELECTRICAL ADJUSTMENT
1. CAUTION
1. Perform adjustment in sequence as listed.
2. Apply a 9 volt DC supply voltage.
2. DC BIAS ADJUSTMENT
Connect a digital voltmeter to test points TP119, 121, 125, 127,
130, 131, 133, 134 on the LED board. Adjust RV101 on the TX
board to obtain an output voltage of 480 ± 5mV on the TX board.
TP119,121,125,127,
130,131,133,134
10kΩ
0.1µ
digital voltmeter
ceramic
3. RF level alignment
Connect an oscilloscope to test points TP119, 121, 125, 127,
130, 131, 133, 134 on the LED board. Adjust RV201 on the TX
board to obtain an output waveform of 960±5mVp-p.
TP119,121,125,127,
130,131,133,134
oscilloscope
Note: Use an oscilloscope with a bandwidth of at lest 200 MHz.
4. RECHECK
The DC bias adjustment made above in 2. may sometime change
(deviate) after the RF level adjustment is made above in 3. So
recheck that the DC bias is at the correct level after making the
RF level alignment. If the DC bias has deviated, realign by re-
peating the adjustment in 2. and 3. above.
• Connection points :
C301
R111
Q355
R216
C207
R100
R107
R210
R215
R101
Q354
R114
C290
Q351
R113
R85
C210
R208
R214
R217
R213
R89
Q357
Q358
R102
C206
Q352
C224
C223
C230
R87
R211
R209
R212
R112
Q362
Q361
Q360
C239
C241
C231
C229
C228
C227
C226
C225
IC206
JC117
C242
Q356
Q353
Q359
R110
JW216
D216
JW221
D17
JW213
JW217
JW204
D211
JW220
JW211
CN903
C351
0
JW212
JW224
JW223
JW209
JW222
JW218
JW225
JW226
D220
JW227
JW215
D13
D14
D15
D16
D9
D8
D7
D6
D5
D208
D209
D210
D214
D213
D212
D219
D218
D217
D215
D221
SW3
SW4
JW214
LED BOARD
D221
VERTUAL
TP121
TP131
TP130
TP133
TP134
TP119
TP127
TP125
TP121
TP119
TP134
TP133
TP131
TP130
TP125
TP127
(pattern)
• Adjustment location:
TX BOARD (SIDE A)
IC12
IC19
RV201: RF LEVEL alignment
RV101: DC BIAS alignment
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13
DP-IF8000
Pin No.
Pin name
I/O
Description
1
P120
I
Error signal input from DIR.
2
P121
I
No audio signal input from DIR.
3
P122
I
EMPHASIS signal input from DIR.
4
P123
I
F0 signal input from DIR.
5
P124
I
F1 signal input from DIR.
6
P125
I
F2 signal input from DIR.
7
P126
I
STATE signal input from DIR.
8
P127
I
Serial data signal input from DIR.
9
VDD
I
Power supply terminal.
10
X2
O
Connect for crystal for main clock oscillator (8MHz).
11
X1
I
Connect for crystal for main clock oscillator (8MHz).
12
VSS
—
Ground Terminal.
13
XT2
—
Not used (OPEN).
14
XT1
—
Not used (Fixed at "L").
15
RESET
I
Reset signal input.
16
P00
O
SPI SLAVE select signal output.
17
P01
O
Decorder CS signal output.
18
P02
O
DIR CS signal output.
19
P03
O
CS signal output for DA converter.
20
P04
O
DIAT latch signal output.
21
P05
I
Serial date input from decoder.
22
P06
—
Not used (OPEN).
23
AVDD
—
Power supply terminal.
24
AVREF0
—
Ground Terminal.
25
P10
I
Not used (OPEN).
26
P11
—
Not used (OPEN).
27
P12
I
Not used (OPEN).
28
P13
I
Not used (OPEN).
29
P14
I
Not used (OPEN).
30
P15
I
Not used (OPEN).
31
P16
—
Not used (OPEN).
32
P17
I
Not used (OPEN).
33
AVSS
—
Analog ground terminal.
34
ANO0/P130
—
Not used (OPEN).
35
ANO1/P131
—
Not used (OPEN).
36
AVREF1
I
Power supply terminal.
37
SI2
I
DIR serial data input.
38
SO2
O
DIR serial data output.
39
SCK2
O
DIR serial clock output.
40
SI1
I
Main serial data input.
41
SO1
O
Main serial data output.
42
SCK1
O
Main serial clock output.
43
P23
I
Main DSP request signal input.
44
P24
—
Not used (OPEN).
45
SI0
I
Serial data input.
46
SO0
O
Serial data output.
SECTION 6
DIAGRAMS
6-1. EXPLANATION OF IC TERMINALS
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DP-IF8000
47
SCK0
O
Serial clock output.
48
P80
I
No audio signal input.
49
P81
O
DSP mute signal output.
50
P82
O
DSP effect signal output.
51 to 55
P83 to P87
O
DSP control signal output.
56 to 61
P40 to P45
O
Reset signal outtput.
62 to 71
P46 to P57
—
Not used (OPEN).
72
VSS
—
Ground Terminal.
73
P60
I
Power ON/OFF Key input.
74
P61
I
INPUT Key input.
75
P62
I
EFFECT Key input.
76
P63
I
OUTPUTKey input.
77
P64
—
Not used (OPEN).
78
WR/P65
I
Not used (OPEN).
79
WAIT/P66
I
Not used (OPEN).
80
WSTB/P67
I
Not used (OPEN).
81
VDD
I
Power supply terminal.
82
P100
O
LED enable signal output.
83
P101
O
LED latch signal output.
84
P102
O
Not used (OPEN).
85
P103
—
Not used (OPEN).
86
P30
O
Audio mute signal output.
87
T01/P31
—
Not used (OPEN).
88
P32
—
Not used (OPEN).
89
P33
O
Main power ON/OFF signal output.
90
P34
O
IF power ON/OFF signal output.
91
P35
O
Selector output for DIR.
92
P36
O
Input select signal output.
93
P37
—
Not used (OPEN).
94
VPP
I
VPP signal input.
95 to 100
P90 to 95
—
Not used (OPEN).
Pin No.
Pin name
I/O
Description
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15
DP-IF8000
Pin No.
Pin name
I/O
Description
1
SCKISP
I
Serial clock signal input.
2
SS
I
SPI SLAVE select signal input.
3
HREQ
O
Host request select signal output.
4
SDO0
O
Serial data output.
5
SDO1
O
Serial data output.
6
SDO2
O
Serial data output.
7
SDO3
I
Serial data input.
8
VCCS
I
Power supply terminal.
9
GNDS
—
Ground terminal.
10
SDO4
I
Serial data input.
11
SDO5
I
Serial data input.
12
FST
I
Transmitter frame sync signal input.
13
FSR
I
Receiver frame sync signal input.
14
SCKT
I
Transmitter serial clock signal input.
15
SCKR
I
Receiver serial clock signal input.
16
HCKT
—
Not used (OPEN).
17
HCKR
—
Not used (OPEN).
18
VCCQL
I
Power supply terminal.
19
GNDQ
—
Ground terminal.
20
VCCQH
I
Power supply terminal.
21
PV12
—
Not used (OPEN).
22
PV11
—
Not used (OPEN).
23
PB15
—
Not used (OPEN).
24
PB14
—
Not used (OPEN).
25
VCCS
I
Power supply terminal.
26
GNDS
—
Ground terminal.
27
PD1
—
Not used (OPEN).
28
PD0
—
Not used (OPEN).
29
TIO0
I
Timer shumit triger signal input.
30
PD13
—
Not used (OPEN).
31
PD10
—
Not used (OPEN).
32
PB9
—
Not used (OPEN).
33
PB8
—
Not used (OPEN).
34
PB7
I
DSP control signal input.
35
PB6
I
DSP control signal input.
36
PB5
I
DSP control signal input.
37
PB4
I
DSP control signal input.
38
VCCH
I
Power supply terminal.
39
GNDH
—
Ground terminal.
40
PB3
I
DSP effect signal input.
41
PB2
I
DSP effect signal input.
42
PB1
I
DSP mute signal input.
43
PB0
O
No audio signal output.
44
RESET
I
Reset signal output.
45
VCCP
I
Power supply terminal.
46
PCAP
I
Capacitor connect terminal for PLL.
47
GNDP
—
Ground terminal.
48
SDI0-1
I
Serial data signal input.
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16
DP-IF8000
Pin No.
Pin name
I/O
Description
49
VCCQH
I
Power supply terminal.
50
FST1
I
Receiver frame sync signal input.
51
AA2
—
Not used (OPEN).
52
CAS
—
Not used (OPEN).
53
DE
I
Transmitter serial clock signal input.
54
CNDQ
—
Ground terminal.
55
EXTAL
I
Exterminal clock signal input (12,2888MHz).
56
VCCQL
I
Power supply terminal.
57
VCCC
I
Power supply terminal.
58
GNDC
—
Ground terminal.
59
FSR1
I
Receiver frame sync signal input.
60
SCKR1
I
Transmitter serial clock signal input.
61
PINIT
—
Ground terminal.
62
TA
—
Ground terminal.
63
BR
—
Not used (OPEN).
64
BB
I
Bus busy signal input.
65
VCCC
I
Power supply terminal.
66
GNDC
—
Ground terminal.
67
WR
—
Not used (OPEN).
68
RD
—
Not used (OPEN).
69 • 70
ADD1 • 0
—
Not used (OPEN).
71
BG
—
Ground terminal.
72 • 73
A0 • 1
—
Not used (OPEN).
74
VCCA
I
Power supply terminal.
75
GNDA
—
Ground terminal.
76 to 79
A2 to 5
—
Not used (OPEN).
80
VCCA
I
Power supply terminal.
81
GNDA
—
Ground terminal.
82 to 85
A6 to 9
—
Not used (OPEN).
86
VCCA
I
Power supply terminal.
87
GNDA
—
Ground terminal.
88 to 89
A10 • 11
—
Not used (OPEN).
90
GNDQ
—
Ground terminal.
91
VCCQL
I
Power supply terminal.
92 to 94
A12 to 14
—
Not used (OPEN).
95
VCCQH
I
Power supply terminal.
96
GNDA
—
Ground terminal.
97 to 99
A15 to 17
—
Not used (OPEN).
100 to 102
D0 to 2
—
Ground terminal.
103
VCCD
I
Power supply terminal.
104
GNDD
—
Ground terminal.
105 to 110
D3 — 8
—
Ground terminal.
111
VCCB
I
Power supply terminal.
112
GNDD
—
Ground terminal.
113 to 118
D9 — 14
—
Ground terminal.
119
VCCD
I
Power supply terminal.
120
GNDD
—
Ground terminal.
121 to 125
D15 — 19
—
Ground terminal.
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17
DP-IF8000
Pin No.
Pin name
I/O
Description
126
VCCQL
I
Power supply terminal.
127
GNDQ
—
Ground terminal.
128
D20
—
Ground terminal.
129
VCCD
I
Power supply terminal.
130
GNDD
—
Ground terminal.
131 to 133
D21 — 23
—
Ground terminal.
134
MODD
—
Not used (Fixed at "L").
135
MODC
I
Mode select / exterminal interrupt request signal input (Fixed at "H").
136
MODB
I
Mode select / exterminal interrupt request signal input (Fixed at "L").
137
MODA
I
Mode select / exterminal interrupt request signal input (Fixed at "H").
138
SD04_1
O
Serial data output.
139
TDO
—
Not used (OPEN).
140
TDI
—
Not used (OPEN).
141
TCK
—
Not used (OPEN).
142
TMS
—
Not used (OPEN).
143
SI
I
SPI master data signal input.
144
SO
—
Not used (OPEN).
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DP-IF8000
18
18
6-2. BLOCK DIAGRAM (1/2)
4
1 48 34 24 23 26 27 28
22 15 14 13 36 35 37 38
16
5
10
67
12
17
91 61 1
2
143
13
50
59
1
2
3
3
4
5
6
7
8
10
11
56
21
15 14 13
7
3
2
16
4
16
3
IC1
D201-221
LED
DISPLAY
IC2
47 46
144 143 1
2
44
12
13
14
15
55
7
6
5
4
4
57 58 59
51 52 53 54 55 50
60 49 48
2
3
4
21
24
20
5 - 19
73
POWER
74
INPUT
SW1
SW2
75
EFFECT
SW3
76
15
OUTPUT
SW4
83
82
44 42 43
X3
8MHz
CONTROL
BUS
1
3
7
14 AIN_L
AIN_R
13
5
LRCK
SCLK
MCLK
XRST
SDOUT
92
68
28
51
5
1-4,13-21,
29-32
6,7,10,11,
22,23,26,27
100-103,
105-109
6,7,10,11,
22,23,26,27
6,7,10,11,
22,23,26,27
110,113-118,
121
72,73,76-79,
82-85,88,89,
92-94,97,98
14
15
60
55
34
35
36
37
40
41
10
11
48
7
53
12
5
6
4
138
VPOUT1
RCS
RINFO
DILRCK
VPOUT2
122-125,128,
131-133
8
8
8
16
P35
DISEL
SCK0
SDO0
INSEL
DEC_DET
DEC_XCS
SCK1
SDO1
SDI1
D5
DSP_HREQ
DSP_XCS
SCK1
SDO1
DEC_XRST
DIH_XRST
DIS_XRST
ADDA_XRST
DSPTMP1
DSPTMP2
DSPTMP3
DSPTMP4
DSPTMP5
DSPEFF
DSP_XRST
DSPMUTE
NOAUDIO
DIE_XRST
ADDA_XRST
DIR_ERR
DIR_NAUD
DIR_EMP
DIR_F0
DIR_F1
DIR_F2
DIR_XST
DIR_DET
P45
P120
P121
P122
P123
P124
P125
P126
P127
P36
X2
X1
P40
P05
P41
P42
P43
P83
P84
P85
P86
P87
P82
P44
P81
P80
D4
DIN0
DATAO
DIN1
DISEL
DISEL
DIR__XRST
DIR__ERR
DIR__NAUD
DIR__EMP
DIR__F0
MCK
LRCK
BCK
MCKADDA
SDI2
SDO2
DIR_XCS
SCK2
DIR__F1
DIR__F2
DIR__XST
DIR__DET
XMODE
ERROR
AUDIO
EMPHA
F0
F1
F2
XSTATE
DATAO
LRCK
BCK
CKOUT
XIN
LRCK
BCK
CKOUT
DO
DI
CE
CL
6
1
7
SDO4
WR
RD
WE
OE
CS
A0
I
A16
D0
I
D7
D8
I
D15
D16
I
D23
AA2
SDO0
SDO1
SDO2
SDO3
SO
SI
SCK
SS
SI
SCK
SS
HREQ
RESET
PB1
PB0
SDO0
RESET
EXTAL
SCKR
SCKT
FSR
FST
FSR
LRCK
BCK
MCK
LRCK
BCK
MCK
FST_1
FSR_1
SCKT
SCKR
SCKT_1
SCKR_1
EXTAL
FB7
FB6
FB5
FB4
PB3
P82
DSPEFF
SDO5_1/SDIO_1
SDO3
SDO4
SDO5
SDO1
FST
SDO4_1/RDI1_1
SDO2
SDO0
OTHSG
CLFSG
SLRSG
FLRSG
DSPTMP1
DSPTMP2
DSPTMP3
DSPTMP4
DSPTMP5
P101
SERIAL-IN
CLOCK
XLATCH
XENABLE
P100
P60
P61
P62
P63
A0
I
A16
I/O0
I
I/O7
I/O0
I
I/O7
I/O0
I
I/O7
DIGITAL
IN-1
OPTICAL
DIGITAL
IN-2
OPTICAL
IC3
LINE AMP
IC20
ADC
IC18(1/2)
SYSYTEM
CONTROL
IC206
DATA DECODER,
LED DRIVER
IC4
DIR
IC13-IC15
RAM
IC8
SELECT SWITCH
IC11
DECODER
IC19
MAIN DSP
UCON
VDD
S101
ATT
0dB -8dB
Q101
J101
LINE
IN
Q102
SDO0
SCK0
LED DRIVER
Q201,202
VDD
OUT15
OUT14
I
OUT0
REG
9V
RESET
< UCON1
VDD
D17
D18
IC13
IC14
IC15
TX MAIN
SECTION (2/2)
A
TX MAIN
SECTION (2/2)
B
L
R
• Signal Path
:LINE(ANALOG)
:LINE(DIGITAL)
3
1
RESET
IC17
VDD
w w w
.
x i a o y u 1 6 3 .
c o m
Q Q
3 7 6 3 1 5 1 5 0
9
9
2
8
9
4
2
9
8
T E L
1 3 9 4 2 2 9 6 5 1 3
9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
Q
TEL 13942296513 QQ 376315150 892498299
TEL 13942296513 QQ 376315150 892498299
http://www.xiaoyu163.com
DP-IF8000
19
19
6-3. BLOCK DIAGRAM (2/2)
IC22
IF AMP
96 DTIN
VPOUT1
RCS
RINFO
DILRCK
VPOUT2
CONTROL
BUS
5
73
71
109 RCS
107 RINFO
98
152 151 153 139 140
17
43 20 19 18
38
16 46 47 37
41
39 40
86
10 1
8
9
6
4
5
104 97 106
LRCKIN
BUFFER
Q201
LED DRIVER
Q354,351,357
RV201
RF LEVEL
RV101
DC
BIAS
3
1
LED DRIVER
Q356,353,359
LED DRIVER
Q362,361,360
LED DRIVER
Q355,352,358
OSCI
DAAOUT
OSCO
120
3
5
VOCT
VCOOUT
FINB
FINA
112
PLVAR
12
VCOIN
6
PFDOUT
AOUT A-
AOUT A+
AOUT B-
AOUT B+
SDATA
SCLK
LRCK
MCLK
M2
M1
M0
XRST
BCK
SCK1
LRCK
MCKADDA
SCK0
SDO0
DAC_XCS
ADDA_XRST
X2
24.576MHz
4
3
113
PRRET
XLAT
SCLK
SWDT
XRST
XRSTS
12.88OUT
BCLK IN
BCLK
SCK0
SDO0
DIH_XRST
DIS_XRST
DATA_LAT
DIAT_LAT
DAC_XCS
DIR_XCS
DEC_XCS
DSP_XCS
DSP_XHREQ
SDO0
SCK0
SDI2
P23
P04
P03
P02
P01
P00
P26/SO0
P27/SCK0
P70/SI2
P71/SO2
P72/SCK2
P20/SI1
P21/SO1
SDO1
SDI1
SCK2
SDO2
MCK
BCK
2
3
6
5
14
15
19
18
7
1
MUTE
Q901,902
RV901
LEVEL
7
1
8
5
3
7
6
2
1
5
3
8
RIPPLE
FILTER
Q903
J901
PHONES
2
4
+1.8V
REG.
IC903
IC905
2
4
1
+3.3V
REG.
IC904
2
4
1
+3.3V
REG.
IC906
1
2
+5.0V
REG.
IC902
1
2
+9V
REG.
IC907
1
2
4
+3.9V
REG.
IC901
1
2
4
+9V
REG.
B+ SWITCH
Q901,902
B+ SWITCH
Q901,902
89
90
42
4
2
DC IN 9V
!
J901
TX LED
D5-8
D9-12
D13-16
D17-20
IC901
PRE DRIVER
IC21
LPF
IC5
DAC
IC10
VCO
IC12
DIAT
IC902
HEADPHONE AMP
UCON VDD
REG 9V
IF 9V
OPT VCC
2
3
6
1
4
5
IC9
BUFFER
P22/SCK1
P30
P33
P34
SRAM
VDD
OPT
VCC
SW
5.0V
IF AMP
VCC
VDD
1.8V
REG
3.3V
AMUTE
MAPOW
IFPOW
IC18 (2/2)
SYSTEM
CONTROL
IC23
INV.
VCC
VCC
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