RT9990 2 DS9990-P01 October 2010 www.richtek.com Preliminary Typical Application Circuit Timing Diagram RT9990 R1 R2 Q1 D1 L1 10µH 22µF x 3 VAVDD 1µF 22µF L2 10µH D2 22µF x 2 VIN 12V VCC 3.3V RESETB 0.1µF Q2 1µF VCC 100 R3 R4 4.7µF 1µF VGL SWB 1µF Q3 1µF SW 1µF 1µF R5 R6 VAVDD VGH C1 R13 C17 C3 CDLY SWB VSENSE FBN RESETB CTRLN SS AGND DLY VL CRST BOOT VIN PGND COMP SW GD CTRLP FBP FB 27, 28 3 6 7 2 4 5 1 23, 24 19 22 21 20 18 17 15 16 25, 26, 29 (Exposed Pad) 14 22µF C10 C9 R8 C11 R9 C12 C13 C5 C18 C19 R12 C7 R16 R14 C20 C21 D4 C22 R15 C23 R10 C14 C15 D3 C16 R11 CCRST C6 1µF TEST 13 VIN VGH AVDD 3ms tDLY VCC VGL Time Time 3ms VIN > UVLO RESETB VCC > 80% tCRST VIN < UVLO VCC < 80% VGH DCOUT RT9990 3 DS9990-P01 October 2010 www.richtek.com Preliminary Functional Pin Description Pin No. Pin Name Pin Function 1 VL Internal Logic Regulator Output. Connect this pin with a decoupling capacitor. 2 BOOT N-MOSFET Gate Drive Voltage for the Buck Converter. Connect a capacitor from the switch node SWB to this pin. 3 SWB Switch Pin of the Buck Converter. 4 CTRLN Base drive of the external NPN transistor for the negative supply VGL. 5 FBN Feedback of the Negative Supply VSS. 6 VSENSE Output Voltage Sense Pin for the Buck Converter. 7 RESETB Voltage Detector Open-Drain Output Pin for VCC. 8, 9, 10, 11, 12 NC No Internal Connection. Should be floating or connected to GND. 13 TEST Test Pin. Should be connected to GND. 14 AGND Analog Ground. 15 DLY Delay Pin to Enable Boost Converter and VGH Charge Pump. 16 CRST VCC Voltage Detector Delay Capacitor Connection. 17 SS Soft-Start for the Boost Converter AVDD. 18 COMP Compensation Pin for the Boost Converter. 19 FB Feedback for the Boost Converter AVDD. 20 FBP Feedback for the Positive Charge Pump VGH. 21 CTRLP Base drive of the external PNP transistor for the positive charge pump VGH. 22 GD Gate drive pin which is used to control an external MOSFET switch to provide input to output isolation of AVDD. 23, 24 SW Switch Pin of the Boost Converter. 25, 26, 29 (Exposed Pad) PGND Power Ground for the Boost Converter AVDD. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. 27,28 VIN Power Input Voltage Pin. RT9990 4 DS9990-P01 October 2010 www.richtek.com Preliminary Function Block Diagram PGND FB COMP Internal Regulator Buck BOOT SWB VSENSE Oscillator VIN CTRLN VGL Regulator FBP Thermal Shutdown CTRLP VIN SS UVLO DLY AGND RESETB CRST GD Boost Sequence Control VDD VGH Regulator SW TEST VL FBN Preliminary Specification iML7991 Programmable Gamma Buffers, DVR & VCOM buffer with Embedded Non Volatile Memory (NVM)  2008, 2009 IML Inc. All rights reserved. Confidential 7991DOC rev0.5 2 Pin Descriptions Pin No. Pin Name Type I/O Type Function 8,31,32 AVDD Power Supply Analog power supply 11,25,29 AGND Ground Ground Analog Ground 15 SDA Digital Input and Open Drain Output I2C Serial Digital Data Input/Output. 14 SCL Digital Input I2C Digital Serial Clock Input 27 VCOM_ADJ Analog Output Adjust sink current output. This pin connects to resistive divider between AVDD and AGND that sets VCOM voltage 30 VCOM_OUT Analog Output Voltage output for VCOM. 28 VCOM_FB Analog Input VCOM feedback signal 26 SET Analog Input Full scale sink current adjustment 16 nWR Digital Input Enable/Disable write data in Non Volatile Memory. nWR = 0, Data can be written to Non Volatile Memory nWR = 1, Data can not be written to Non Volatile Memory 1 OUT1 Analog Output Analog output reference-1 2 OUT2 Analog Output Analog output reference-2 3 OUT3 Analog Output Analog output reference-3 4 OUT4 Analog Output Analog output reference-4 5 OUT5 Analog Output Analog output reference-5 6 OUT6 Analog Output Analog output reference-6 7 OUT7 Analog Output Analog output reference-7 18 OUT8 Analog Output Analog output reference-8 19 OUT9 Analog Output Analog output reference-9 20 OUT10 Analog Output Analog output reference-10 21 OUT11 Analog Output Analog output reference-11 22 OUT12 Analog Output Analog output reference-12 23 OUT13 Analog Output Analog output reference-13 24 OUT14 Analog Output Analog output reference-14 17 DVDD Power Supply Digital voltage power supply 13 DGND Ground Ground Digital Ground 12 BANK_SEL Digital Input Internal A/B bank select, LO=Bank A, HI=Bank B 9 STATIC_HI Analog Input Hi reference for output voltage 10 A0 Digital Input Device address select (A0 low address 0x74, A0 High address 0x75) TP Thermal Pad - Thermal pad connected to AGND Preliminary Specification iML7991 Programmable Gamma Buffers, DVR & VCOM buffer with Embedded Non Volatile Memory (NVM)  2008, 2009 IML Inc. All rights reserved. Confidential 7991DOC rev0.5 3 Function Block Diagram I2C Interface Logic SCL SDA nWR A0 Non- Volatile Memory Timing Controller Bank-B 10 bits Bank-A 14 Sets Bank Select Controller DAC OUT1 DAC OUT2 DAC OUT3 DAC OUT4 DAC OUT13 DAC OUT14 BANK_SEL STATIC_Hi GND VCOM_FB VCOM_OUT VCOM_ADJ SET DAC VCOM 7 bits AVDD I2C Interface Logic SCL SDA nWR A0 Non- Volatile Memory Timing Controller Bank-B 10 bits Bank-A 14 Sets Bank Select Controller DAC OUT1 DAC OUT2 DAC OUT3 DAC OUT4 DAC OUT13 DAC OUT14 BANK_SEL STATIC_Hi GND VCOM_FB VCOM_OUT VCOM_ADJ SET DAC VCOM 7 bits AVDD I2C Interface Logic SCL SDA nWR A0 Non- Volatile Memory Timing Controller Bank-B 10 bits Bank-A 14 Sets Bank Select Controller DAC OUT1 DAC OUT1 DAC OUT2 DAC OUT2 DAC OUT3 DAC OUT3 DAC OUT4 DAC OUT4 DAC OUT13 DAC OUT13 DAC OUT14 DAC OUT14 BANK_SEL STATIC_Hi GND VCOM_FB VCOM_OUT VCOM_ADJ SET DAC VCOM 7 bits AVDD 3 DS8922-P00 May 2012 www.richtek.com RT8922 Preliminary © Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Power Off Sequence Power On Sequence VULVO = 1.8V VGON VSS VGOFF VGOAL or VSS VGOFF VIN VGON XON STH1 or STH2 CKH1 to CKH6 LC1 or LC2 GND GND GND GND GND 10ms VIN VGON STH1 or STH2 CKH1 to CKH6 XON LC LC1 LC2 VGOFF VGON VGOFF VSS VGOAL or VSS VGON VGOFF VUVLO = 2V SHD = 1V Timing Diagram 4 DS8922-P00 May 2012 www.richtek.com RT8922 Preliminary © Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Pin No. Pin Name Pin Function 1 TERMINATE Level Shifter Input Signal (turns off all buffers in blanking time). 2 LC Level Shifter Input Signal (low frequency). 3 ROTATE Setting Pin for Rotate Output. VIN : CKH6 (or CKH4) to CKH1 in sequence. GND : CKH1 to CKH6 (or CKH4) in sequence. 4 RATIO Ratio Setting for VCOM Temperature Compensation. 5 VCOMADJ VCOM Adjusted by Temperature Compensation. 6, 41 (Exposed Pad) AGND Analog Ground for Logic Block and Linear Regulators. The exposed pad must be soldered to a large PCB and connected to AGND for maximum power dissipation. 7 GOAL Low Level of GOA. 8 XON Discharge Function for Liquid Crystal Capacitor. 9 VSS Negative Power Supply. 10 VGOFF Gate-Off Power Supply. 11 STH2 Level Shifter Output Signal (Start pulse for ROTATE). 12 to 14, 16 to 18 CKH6 to CKH4, CKH3 to CKH1 Level Shifter Output. 15, 20, 23 NC No Internal Connection. 19 LC2 Level Shifter Output Signal (low frequency 2). Inverse of LC. 21 LC1 Level Shifter Output Signal (low frequency 1). Connect to the FB of AVDD. 22 STH1 Level Shifter Output Signal. 24 VGON Gate-On Power Supply. 25 SHD Trigger of Protection Functions. 26 SET3 Setting Pin for Clock Interval. VIN : no time interval. GND, Floating : some time interval. 27 SET2 Setting Pin for Pre-charge Selection. VIN : 1 line. GND : 2 lines. Floating : No pre-charge. 28 SET1 Setting Pin for Phase Selection. VIN : 6 phases. GND, Floating : 4 phases. 29 PMS Power MOSFET Supply. 30 LXG Switch Node of Boost Converter. 31 PGND Power Ground. PGND is connected to the power N-MOSFET. 32 FBG Boost Converter Feedback Signal. 33 COMPG Error Amplifier of Boost Controller Compensation. Connect series RC from COMPG to AGND. 34 REF Internal Reference Voltage Output (2V typ.). 35 VT Temperature Sensing. 36 END Setting the High Level for VGON Temperature Compensation. 37 SET4 Setting Pin for 3D Mode Enable. VIN : 3D Mode. GND or floating : 2D Mode. Functional Pin Description 5 DS8922-P00 May 2012 www.richtek.com RT8922 Preliminary © Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Pin No. Pin Name Pin Function 38 VIN Supply Voltage Input. 39 VST Level Shifter Input Signal (start pulse). 40 VCE Level Shifter Input Signal (condensed clock). 6 DS8922-P00 May 2012 www.richtek.com RT8922 Preliminary © Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Function Block Diagram PWM Controller (Boost) LXG PGND COMPG FBG VIN PMS Temperature Compensation Logic SHD Function Logic REF REF VCOM Control Logic RATIO VCOMPADJ + - 1.12V SHD Control Logic VGOFF STH1 VGON VGOFF VGON STH2 VGOFF VGON LC1 VST VGON LC2 VGOFF LC Decoding Logic VSS VGON CKH1 VSS VGON CKH3 VSS VGON CKH5 VSS VGON VSS VGON VGON VSS CKH2 CKH4 CKH6 XON Controller VGON GOAL XON AGND ROTATE SET1 SET2 SET3 SET4 VCE TERMINATE VT END