安桥ONKYO DV-SP302 DVD播放器电路图
DV-SP302
SERVICE MANUAL
SERVICE MANUAL
DVD PLAYER
Black, Silver and Golden models
MODEL DV-SP302
Ref. No. 3814
092004
120V AC, 60Hz
CDD
CUA, CUT,
CUK, CUR
100-240V AC, 50/60Hz
RC-575DV
SAFETY-RELATED COMPONENT
WARNING!!
THE MARK FOUND ON SOME COMPONENT
PARTS INDICATES THE CRITICAL FOR RISK OF
FIRE AND ELECTRIC SHOCK.
WHEN REPLACING, BE SURE TO USE PARTS OF
IDENTICAL DESIGNATION.
MAKE LEAKAGE-CURRENT OR RESISTANCE
MEASUREMENTS TO DETERMINE THAT EXPOSED
PARTS ARE ACCEPTABLY INSULATED FROM THE
SUPPLY CIRCUIT BEFORE RETURNING THE
APPLIANCE TO THE CUSTOMER.
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DV-SP302
SPECIFICATIONS
DVD Player
Power supply
AC 120 V, 60 Hz (North America models)
AC 100-240 V, 50/60 Hz (Other models)
Power consumption
16 W
Weight
6.6 lbs, 3.0 kg
External dimensions (W x H x D)
17-1/8" x 3-3/16" x 11-1/8"
435 x 82 x 283 mm
Signal system
PAL/NTSC
Frequency response
Digital output
4 Hz to 22 kHz (48 kHz sampling)
DVD linear sound
4 Hz to 44 kHz (96 kHz sampling)
Signal-to-noise ratio (digital output)
More than 90 dB
Audio dynamic range (digital output)
More than 90 dB
Harmonic distortion (digital output)
Less than 0.008%
Wow and flutter
Below measurable level
Outputs
Video output
1.0 V (p-p), 75 ohm negative sync., pin jack
S-video output
(Y) 1.0 V (p-p), 75 ohm negative sync.,
(C) 0.286 V (p-p), 75 ohm Mini DIN 4-pin
PAL: (C) 0.300 V (p-p)
Component video output
(Y) 1.0 V (p-p), 75 ohm negative sync.,
(PB)/(PR) 0.7 V (p-p), 75 ohm pin jack
Audio output
Optical digital output
-22.5 dBm, optical connector
Coaxial digital output
0.5 V (p-p), 75 ohm pin jack
Analog output
2.0 V (rms), 100 ohm pin jack (L, R)
Specifications and features are subject to change without notice.
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DV-SP302
SERVICE PROCEDURE-1
SAFETY CHECK
(Only U.S.A. model)
After correcting the original service problem perform the
following safety check before releasing the set to the customer
Connect the insulating-resistance tester between the plug of
power supply cord and terminal GND on the back panel.
Specifications: More than 10M ohm at 500V
The lightning flash with arrowhead symbol, within an equilateral triangle, is
intended to alert the user to the presence of uninsulated "dangerous voltage"
within the product's enclosure that may be of sufficient magnitude to constitute
a risk of electric shock to persons.
The exclamation point within an equilateral triangle is intended to alert the user
to the presence of important operating and maintenance (servicing) instruction
in the literature accompanying the appliance.
RISK OF ELECTRIC SHOCK
DO NOT OPEN
WARNING
AVIS
RISOUE DE CHOC ELECTRIQUE
NE PAS OUVRIR
This unit contains a semiconductor laser system and is classified as a
“CLASS 1 LASER PRODUCT”. So, to use this model properly, read
this Instruction Manual carefully. In case of any trouble, please contact
the store where you purchased the unit. To prevent being exposed to the
laser beam, do not try to open the enclosure.
CAUTION:
VISIBLE LASER RADIATION WHEN OPEN AND INTERLOCK
FAILED OR DEFEATED. DO NOT STARE INTO BEAM.
CAUTION:
THIS PRODUCT UTILIZES A LASER. USE OF CONTROLS OR
ADJUSTMENTS OR PERFORMANCE OF PROCEDURES OTHER
THAN THOSE SPECIFIED HEREIN MAY RESULT IN
HAZARDOUS RADIATION EXPOSURE.
The label on the right is
applied on the rear
panel except for USA
and Canadian models.
1. This unit is a CLASS 1 LASER PRODUCT and employs a laser
inside the cabinet.
2. To prevent the laser from being exposed, do not remove the
cover. Refer servicing to qualified personnel.
“CLASS 1 LASER
PRODUCT”
LASER CAUTION
CAUTION
VISIBLE AND INVISIVLE LASER RADIATION
WHEN OPEN DO NOT STARE INTO THE BEEM OR
VIEW DIRECTLY WITH OPTICAL INSTRUMENTS.
DO NOT PRESS ON THIS SURFACE
1.Remove the solder of Laser Diode shorting
1-1
Remove the bracket magnet.
1-2
Shorting the short land with solder.
1-3
Remove the FFC and other connectors.
2. Factory setting (Initial setting)
2-1 Open the tray. Press 2 second the search button and
power key on remote controller (RC-575DV).
2-2 Displayed version of firmware on the FL tube.
2-3. At above condition, turn off the mechanical power switch.
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Bottom side
Fig-1
DV-SP302
SERVICE PROCEDURE-2
Replace the DVD mechanism
1. Remove the top cover (six screws)
2. Remove two screws of both side of front panel.
3. Remove the bracket mecha. (two screws).
4. Shift the cam slider on bottom side. (See Fig-1)
5. Remove the tray.
6. Remove FFC, connector and one screw.
7. A tray is drawn out extending a nail. (See Fig-2)
Tray
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EXPLODED VIEW
A
1
2
3
4
5
B
C
D
S7 x2
S6
10
9
8
7
6
38
S6
5
4
S2 x 4
34
37
16
11
S2 x 2
4
1
4
2
3
S5
x 3
35
S2 x 2
39
1) Insert a plate in a panel front. Thereafter
2) Insert a wire in a hole of palte
and do soler.
39
38
40
S3 x 2
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DV-SP302
E
F
G
H
12
13
14
15
4
S5 x 11
S3
17
18
S3
17
18
S2 x 2
S3
17
18
19
20
21
S2 x 4
S2
22
23
24
25
26
27
28
S8
S4 x 11
30
29
S1 x 3
S2 x 2
31
36 x 3
32
S3 x 2
33
4
S3
18
17
40
S1 : 3 x 18 W/ Washer
S2 : 3 x 8 ZNY/ BH
S3 : 3 x 10 BK/ BH
or 3 x 8 Silver/ BH
S4 : 3 x 10 BK/ BH DOT
S5 : 2.6 x 8 ZNY/ PH
S6 : 3 x 8 BK/ FH
S7 : 3 x 10 BK/ BH
or 3 x 8 W/ Washer
S8 : 3 x 6 BK/ BH
S3 x 3
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DV-SP302
EXPLODED VIEW
A
1
2
3
4
5
B
C
D
E
F
G
H
S7 x2
S6
12
13
14
15
4
S5 x 11
S3
17
18
S3
17
18
S2 x 2
S3
17
18
19
20
21
S2 x 4
S2
22
23
24
10
9
8
7
6
38
S6
5
4
25
26
27
28
S8
S4 x 11
30
29
S1 x 3
S2 x 2
31
36 x 3
32
S3 x 2
33
S2 x 4
34
37
16
11
S2 x 2
4
1
4
2
3
S5
x 3
35
S2 x 2
39
1) Insert a plate in a panel front. Thereafter
2) Insert a wire in a hole of palte
and do soler.
39
38
S3
18
17
40
40
S1 : 3 x 18 W/ Washer
S2 : 3 x 8 ZNY/ BH
S3 : 3 x 10 BK/ BH
or 3 x 8 Silver/ BH
S4 : 3 x 10 BK/ BH DOT
S5 : 2.6 x 8 ZNY/ PH
S6 : 3 x 8 BK/ FH
S7 : 3 x 10 BK/ BH
or 3 x 8 W/ Washer
S8 : 3 x 6 BK/ BH
S3 x 3
S3 x 2
w w w
.
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DV-SP302
BLOCK DIAGRAM
FRONT DISPLAY SECTION
DV-SP302
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BLOCK DIAGRAM
OVERALL
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DV-SP302
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DV-SP302
BLOCK DIAGRAM
OVERALL
w w w
.
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c o m
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SCHEMATIC DIAGRAM
U20 : DVD MAIN CIRCUIT BOARD-2/2
A
1
2
3
4
5
B
C
D
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DV-SP302
E
F
G
H
From Power supply unit
To Output board
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SCHEMATIC DIAGRAM
U20 : DVD MAIN CIRCUIT PC BOARD-2/2
A
1
2
3
4
5
B
C
D
From Front board
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DV-SP302
E
F
G
H
150R-03
150P-03
150P+
150R-03
Y
PB (UDAC)
PR (CDAC)
Y (YDAC) COMP.
Y (YDAC) SVIDEO
CVBS (VDAC)
C (FDAC)
V-MUTE
Pb
PR
CV
C
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SCHEMATIC DIAGRAM
A
1
2
3
4
5
B
C
D
U4 : FRONT DISPLAY PC BOARD
U4-1 : FL TUBE PC BOARD
U4
U4-
To Power supply unit
From Remote
sensor board
From Key
switch board
From FL tube b
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DV-SP302
E
F
G
H
4-2 : KEY SWITCH PC BOARD
-4 : REMOTE SENSOR PC BOARD
U21 : OUTPUT TERMINAL PC BOARD
U4-3 : STANDBY SWITCH PC BOARD
To FL display board
e board
To DVD main board
To DVD
main board
Optical
Coaxial
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TEL 13942296513 QQ 376315150 892498299
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DV-SP302
SCHEMATIC DIAGRAM
A
1
2
3
4
5
B
C
D
E
F
G
H
U4 : FRONT DISPLAY PC BOARD
U4-1 : FL TUBE PC BOARD
U4-2 : KEY SWITCH PC BOARD
U4-4 : REMOTE SENSOR PC BOARD
U21 : OUTPUT TERMINAL PC BOARD
U4-3 : STANDBY SWITCH PC BOARD
To Power supply unit
From Remote
sensor board
To FL display board
From Key
switch board
From FL tube board
To DVD main board
To DVD
main board
Optical
Coaxial
w w w
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TEL 13942296513 QQ 376315150 892498299
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DV-SP302
SCHEMATIC DIAGRAM
U20 : DVD MAIN CIRCUIT BOARD-2/2
A
1
2
3
4
5
B
C
D
E
F
G
H
From Power supply unit
To Output board
w w w
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DV-SP302
SCHEMATIC DIAGRAM
U20 : DVD MAIN CIRCUIT PC BOARD-2/2
A
1
2
3
4
5
B
C
D
E
F
G
H
From Front board
150R-03
150P-03
150P+
150R-03
Y
PB (UDAC)
PR (CDAC)
Y (YDAC) COMP.
Y (YDAC) SVIDEO
CVBS (VDAC)
C (FDAC)
V-MUTE
Pb
PR
CV
C
w w w
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DV-SP302
PCBOARD CONNECTION DIAGRAM
DV-SP302
From power
supply board
POWER SUPPLY UNIT
FL TUBE
BOARD
DVD MAIN BOARD
MECHA.
PICK-UP
CMS-S71SG6C
OUTPUT TERMINAL BOARD
31
U21
U20
U4-2
KEY
SWITCH BOARD
U4-1
U4-4
U4-3
STANDBY
SWITCH BOARD
REMOTE
SENSOR BOARD
U4 FRONT DISPLAY BOARD: (U4-1) + (U4-2) + (U4-3) + (U4-4)
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DV-SP302
PRINTED CIRCUIT BOARD VIEW FROM COMPONENT SIDE-3
R702
R701
R704
R703
R606
R608
R609
D601
R607
Q601
R906
R904
R903
R902
R901
1
13
10
5
50
45
40
39
35
30
14
20
IC91
C905
C943
C942
C941
C940
C939
C938
C937
C936
C935
C934
C933
C932
C931
C930
C929
C928
P16 P15 P14 P13 P12 P11 P10
P9
P8
P7
P6
P5
P4
P3
P2
P1
C924
C925
C927
C926
R932
C922
C921
C920
C919
R910
C923
1 G 2 G 3 G 4 G 5 G 6 G 7 G 8 G 9 G 1 0 G 1 1 G 1 2 G
C917
C916
C918
R931
C902
R919
C904
R909
C901
U4 : FRONT DISPLAY BOARD
U4-1 : FL TUBE BOARD
U4-2 : KEY SWITCH BOARD
U4-4 : REMOTE SENSOR BOARD
U4-3 : STANDBY SWITCH BOARD
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DV-SP302
PRINTED CIRCUIT BOARD VIEW-1
U20 DVD MAIN BOARD-1
Top view
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DV-SP302
PRINTED CIRCUIT BOARD VIEW-2
U20 DVD MAIN BOARD-2
Bottom view
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2
9
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0
5
1
5
1
3
6
7
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DV-SP302
PRINTED CIRCUIT BOARD VIEW FROM SOLDERING SIDE-4
U21 OUTPUT TERMINAL PC BOARD
1
4
5
JK85
2
6
3
JK84
C812
JK82
Component side view
CN83
C802
IC86
JK81
JK83
CN81
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DV-SP302
PRINTED CIRCUIT BOARD VIEW FROM SOLDERING SIDE-5
U21 OUTPUT TERMINAL PC BOARD
Soldering side view
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DV-SP302
IC BLOCK DIAGRAM/ TERMINAL DESCRIPTION
IC6 : BA5954 MOTOR DROVER
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DV-SP302
IC BLOCK DIAGRAM/ TERMINAL DESCRIPTION
IC2 : ES6603 DVD SERVO F/E-(1)
ES6603S
1
13
13
26
26
2
3
4
5
6
7
8
9
10
11
12
12
25
25
24
24
23
23
22
22
21
21
20
20
19
19
18
18
17
17
1 4
1 5
16
16
29
29
31
31
32
32
28
28
27
27
30
30
55
55
56
56
57
57
58
58
59
59
60
60
61
61
62
62
63
63
64
64
52
52
50
50
49
49
53
53
54
54
51
51
4 8
36
36
47
46
45
44
43
42
41
40
39
38
37
37
3 5
3 4
33
33
RX
RX
MEV
EV
VNA
NA
FNN
NN
FNP
NP
DIPIP
DIN
IN
BYP
YP
R FAC
AC
VPA
PA
AIPIP
AIN
IN
ATON
ON
ATOP
OP
R FS IN
IN
R FDC
DC
ME VO
VO
MIN
IN
ML
MLPF
PF
MB
MB
MP
MP
MIRR
RR
LDON
ON
VNB
NB
CDPD
PD
DVDPD
PD
CDLD
LD
DVDLD
LD
VC
VC
VPB
PB
CD_E
_E
CD_F
_F
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DV-SP302
IC BLOCK DIAGRAM/ TERMINAL DESCRIPTION
IC2 : ES6603 DVD SERVO F/E-(2)
Name
Pin Numbers
I/O
Definition
DVDRFP,
DVDRFN
1, 2
I
Differential RF signal attenuator inputs.
A2, B2, C2, D2
3:6
I
AC coupled photo detector interface inputs for the differential phase detector (DPD)
from the main beam photo matrix.
CP, CN
7, 8
—
Differential phase tracking low-pass filter pins. Connect CP to CN via capacitors.
D, C, B, A
9:12
I
Photo detector interface inputs from the main beam photo matrix.
CD_D, CD_C,
CD_B, CD_A
13:16
I
CD photo detector interface inputs from the main beam photo matrix.
CD_F, CD_E
17, 18
I
CD photo detector interface inputs from the CD side beam photo detector; used for
CD tracking detection.
VPB
19
P
Servo block power supply.
VC
20
O
Reference voltage out (VPB/2). Output impedance is less than 50
DVDLD
21
O
DVD APC output; controls laser power for DVD.
CDLD
22
O
CD APC output; controls laser power for CD.
DVDPD
23
I
DVD APC input.
CDPD
24
I
CD APC input.
VNB
25
G
Servo block ground.
LDON
26
I
APC On/Off control. A high level activates LD output. (open is low)
MIRR
27
O
Mirror detect output.
MP, MB
28, 29
I
Mirror top and bottom hold pins.Connected to VPB pin 19 via capacitors.
MLPF
30
I
Mirror low-pass filter pins. Connected to VPB pin 19 via a capacitor.
MIN
31
I
RF input signal for mirror. AC coupled inputs for the mirror detection circuit from
MEVO pin 32.
MEVO
32
O
RFDC bottom envelope out. Pull-In or bottom clamped RF envelope signal output
for mirror detection.
LINK
33
I,O
Linking Signal In/Mirror Monitor Out. In the linking area, the mirror and tracking
error outputs are disabled when this pin goes high. When the monitor output signal
is selected by the Control H register, mirror-related signals can be observed.
DFT
34
O
Defect output. When the Pull-In signal level is below the detection level, or when
the RF signal level is below the detection level, the DFT output goes high. The
defect output is selected by the serial port.
TPH
35
I
Pull-In top hold. Connected to VPB pin 19 via a capacitor.
V125
36
O
1.25V servo block reference voltage output.
V25
37
P
2.5V servo output reference power supply.
PI
38
O
Pull-In signal out. The summing signal output of A, B, C, D, or CD_A, CD_B, CD_C,
or CD_D. Reference to V25/3.
TE
39
O
Tracking error output reference to V125 pin 36.
FE
40
O
Focusing error output reference to V125 pin 36.
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DV-SP302
IC BLOCK DIAGRAM/ TERMINAL DESCRIPTION
IC2 : ES6603 DVD SERVO F/E-(3)
CE
41
O
Cen
enter r error r ou
output t referen
ence t to V
V125 p
pinin 3
36.
6.
MNTR
42
O
Mon
onitor r ou
out t sigignalal. . Outpu
put t is s selelectablele b
by r reg
egister s setttting
ngs.s.
LCN, , LCP
CP
43
43, , 44
I
Lens
ns s shihift
ft offse
set t cancella
llation
on lolow-pas
ass f fililter r pinins. C
Connec
nect t LCN t to L
LCP v viaia a
a capa
pac-
c-
itor.r.
V33
45
P
3.3V
V ou
outpu
put t bu
buffers po
power r supp
pply.y.
SCLK
46
I
Serialal c clock
ck fr
from
om E
ES66x8.
8.
SDAT
ATA
47
I/I/O
Serialal da
data I/
I/O.
O.
SDEN
48
I
Serialal d
data e
enab
ablele. E
. Enabled
ed by
by an
an ac
active
ve-high
gh s sign
gnal.l.
RX
49
I
Reference
ce r resis
sistor. . Connec
nected
ed t to g
groun
und v viaia a
a 12
12.0k
0k , , 1%
1% r resis
sistor....
MEV
50
I
RFDC bo
bottttom e
enve
velope
ope. . Connec
ected
ed t to V
VPA p
pinin 58
58 v viaia a
a c capacicitor.r.
VNA
51
G
RF b
blolock
ck a
and
nd se
serialal po
port t ground.
d.
FNN, F
, FNP
52, 5
53
O
Differentialal ou
outputs o
of f equa
ualize
zer/f/fililter.r.
DIP, D
DIN
54
54, , 55
I
Differen
entialal a
analog
og inpu
nputs t to t the
he R
RF s sing
nglele-end
nd ou
output t bu
buffer and
nd f fullll w
wave
ve r rec
ectifier.r.
BYP
56
I
AGC a
amplilifieier r gainin b
bypass. T
Tied
ed t to V
VPA
A viaia a
a capac
acitor.r.
RFAC
57
O
Sing
nglele-ended
ed R
RF
F ou
outpu
put.
t.
VPA
58
P
RF b
blolock
ck a
and
nd se
serialal po
port t po
power s supplply.y.
AI
AIP, A
AIN
59
59, , 60
I
Differentialal A
AGC a
amp
mplifieier r inp
nputs.s.
ATON, , ATOP
61
61, , 62
O
Differentialal a
attttenuator o
outpu
puts.s.
RFSI
SIN
63
I
Sininglele-ended
ed R
RF
F signa
gnal a
attenua
uator r inp
nput.t.
RFDC
64
O
Sing
nglele-ended
ded R
RF summ
mming
ng ou
output.t.
Name
Pin
n Numbers
I/I/O
Definition
on
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DV-SP302
DVDRFP
DVDRFN
BYP
FULL WAVE
RECTI
F
IER
D IN
AGC
CHARGE
PUMP
PROGRAMMABLE
EQUALIZER
FILTER
DIFFERENTIATOR
FN P
FN N
AGC
RX
A
B
C
D
GCA
GCA
GCA
GCA
3
A + D
B + C
FE
PI
SUM
Amp.
R FAC
RFSIN
MUX
LPF
TE
MUX
CD/DVD
A2
B2
C2
D2
EQ
EQ
EQ
EQ
PHASE
DETECTOR
PHASE
DETECTOR
Comp.
GCA
GCA
GCA
GCA
3
CD_E
CD_F
CE
CN
CP
DFT
RFDC
MIN
D V D LD
C D LD
M LP F
M P
M B
DVDPD
CDPD
LD H/L
Dual APC
MIR R
SDEN
SCLK
SERIAL PORT
REGISTER
V125
VC
VCI for servo input
SIGR b3
APC SEL
DVD/CD
V P A
V P B
V N A
VN B
RFCR b7-6
2
2
IMPUT
BIAS
LPF
Buff
TE
RST
+-3dB
V33
V33 for Output buff
M E V
M E V O
Offset
cancel
PIOR b4-0
PI offset
5
CP/CN
Low Imp
AGC HOLD
INPUT IMP SEL
LPF
Clamp
& Env
Level
DAC
2
GCA
GCA
GCA
TRCR2 b3-0
3B
4
SEL
CD_A
CD_B
CD_C
CD_D
GCA
GCA
GCA
GCA
w/LPF
AGCO
70kHz
70kHz
for TE,FE & CE output ref.
PII
+/- 4dB
MUX
w/LPF
w/LPF
w/LPF
RFCR b2-0
3
3
SSOUT
B + D
A + C
A
B
C
D
CD/DVD
CDR b4
CCR b5
INPUT SEL
INPUT IMP SEL
RFCR b2-0
TRCR2 b6-4
DPD EQ
TRCR b6
DPD COMP HYS ON
PDCR b3
TRCR2 b7
PDCR b3
CTCR b3-0
CO gain
CBR b1-0
RFCR b3
CAR b3-2
SIGDET
RFCR b5-4
FCCR b6-0
FBCR b6-0
CAR b1-0
Env/Clamp
(CDR b5=1)
6dB is added
@high gain mode
(CDR b5=1)
12dB is added
@high gain mode
CONTROL
Signals
To each block
CDR b3
VC
2
Offset
cancel
CER b4-0
CE offset
4
GCA
0-+8dB,4bit
4
Offset
cansel
CCR b4-0
FE offset
5
GCA
+/- 6dB 4bit
4
ATOP
ATON
ATT
4
SIGR b7-4
ATT
AIN
AIN
AIP
Offset
cancel
TRCR b5-0
TR offset
6
GCA
3
CFR b7-5
TR Gain
GCA
FOCR b7-4
FS gain
4
+/- 4dB
MNTR
MON
SEL
CDR b6
HLDEN
FE
SEL
CE
V25
V125
V25/3
3
Tenvb
PIOR b7-5
CBR b5-4
TE MASK sel
LD ON
TOPHLD
TOPHLD
V25
V25/2
TOP HLD
BTM ENV
BTM HLD
TOP ENV
ATT
ATT
MUX
PI
TE
MUX
VC
PII
A G C O
Ten vb
MRCR2 b7 -0
droop rate
control
4D
SUM
MUX
offset
MUX
Vref
Btm clamp
& clip
MUX
MUX
Btm Env
CBR b3-2
TOPHLD
2
DAC
COMP
CTCR b7
BCA DET
TPH
2
D IP
LCN
LCP
SUB
CFR b4
CEFDB
CFR b2-0
CE-ATT
LPF
ATT
Pol.sel
Buf(-12dB)
3
GCA
CGR b5-4
Gain
LIN K
CDR b7
LINKEN
CFR b3
CEPOL
CCR b7
DISK DET
SDATA
FOCR b3-0
FO Gain
RESUM
2
14
CDR b5
High gain
AGC BT M EN V
CTCR b5-4
MEVO SEL
2
CHR b7-6
Mirr Defect
Comp ATT
2
MRCR b6-4
Mirr Comp
ATT Level
3
@high gain mode
SIGR b2-0
(CDR b5=1)
12dB is added
(CDR b5=1)
@high gain mode
SIGR b2-0
12dB is added
CGR b1
OUTPUT INHIBIT
CGR b0
OUTPUT INHIBIT
CDR b2
V25/3
for PI output ref.
IC BLOCK DIAGRAM/ TERMINAL DESCRIPTION
IC2 : ES6603 DVD SERVO F/E-(4)
Block diagram
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DV-SP302
IC BLOCK DIAGRAM/ TERMINAL DESCRIPTION
IC10 : ES6629 VIDEO PROCESSOR-(1)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
SLEGN
AVDD3_DA
PHOI
FGIN
TESTDA
TRACK
FDO
DCS1#
DCS0#
DB4
DRAS0#
DB5
IREF
RFIP
DSSLV
RFIN
VREF09
VREF15
VD33
VS33
WBLCLK
SPD_DOBM/SEL_PLL3
SPDIF_IN
VREF21
LCS1#
VDD
VD33
LA0
LCS3#
LD7
DB1
DB2
VD33
DB3
DWE#
DSCK_EN/DOE#
VSS
DB0
VS33
VD33
VID_XI
VID_XO
CLK
DMA0
DMA1
VD33
DMA2
DMA8
VS33
DMA4
DMA5
DMA6
DMA7
DMA10
VS33
DMA9
DMA3
VD33
DMA11
DCAS#
VDD
DRAS1#
DB15
DB14
VS33
DB6
DB7
LD1
VD33_PL
VS33
RWS
RSD
DB13
DB12
DB11
DB10
DB9
DB8
DSCK
RBCK
LD5
VD33
LD3
LOE#
VS33
LA5
LA4
LA8
VSS
LA10
LA14
VD33
LA16
LA18
LA20
LD6
LD4
VS33
LD2
LWRLL#
LA3
LA6
LA7
VDD
LA9
LA11
LA15
VS33
LA17
LA19
LA21
LD0
VSS
LCS0#
LCS2#
LA1
LA2
VD33
LA12
LA13
DQM
VD33
IPIN
AVDD3_DS
AVDD3_AD
RFRP
VDD
VSS
FLAG3
FLAG2
FLAG1
FLAG0
IP1
WBL
CEI
TEI
AVSS_AD
FEI
SBAD
TESTAD
TEXI
IP2
TBCK
MCLK
TSD3
TSD2
VS33
TWS/SEL_PLL2
UDAC/YUV0
CDAC/YUV2
TSD0/SEL_PLL0
TSD1/SEL_PLL1
YDAC/YUV5
VS33_DA
VD33_DA
VDAC/YUV6
FDAC/YUV7
RSET/YUV4
COMP/YUV3
VREF/YUV1
VS33_PL
LG
TRAY
RFRPCTR
AVSS_DS
SCSJ
SDATA
RESET#
EAUX2
EAUX3
AVSS_PL
PDOFTR1
PLLFTR2
SCLK
VD33
GPIO7
EAUX1
I2CDATA/AUX0
C2PO/AUX4
FTROPI
VREF0
DFCT
VS33
GPIO6
EAUX0
I2C_CLK/AUX1
AUX5
AVDD3_PL
AWRC
LDC
GPIO9
GPIO5
VSS
IOW#/HSYNC#/AUX2
AUX6
PLLFTR1
AVSS_DA
SPDON
GPIO8
GPIO4
VDD
IOR#/VSYNC#/AUX3
IR/AUX7
SPINDLE
FOCUS
SLEGP
VS33
ES6629
DRAS2#
PINOUT DIAGRAM
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DV-SP302
IC BLOCK DIAGRAM/ TERMINAL DESCRIPTION
IC10 : ES6629 VIDEO PROCESSOR-(2)
PIN DESCRIPTION
Names
Pin Numbers
I/O
Definitions
VD33
1, 10, 19, 35, 44,
53, 62, 79, 96, 126,
185
P
I/O power supply.
VID_XI
2
I
Crystal input.
VID_XO
3
O
Crystal output.
CLK
4
I
System clock.
DMA[11:0]
5:8 11:17, 20
O
DRAM address bus.
VS33
9, 18, 34, 43, 52,
61, 78, 95, 119, 127,
186, 208
G
Ground for I/O power supply.
DCAS#
21
O
DRAM column address strobe (active-low).
DCS[1:0]#
22, 23
O
DRAM chip select (active-low).
DRAS[2:0]#
24, 25, 28
O
DRAM row address strobe (active-low).
VSS
26, 70, 86, 137, 197
G
Ground for core power supply.
VDD
27, 71, 87, 138, 198
P
Core power supply.
DSCK_EN
29
O
DRAM clock enable output.
DOE#
O
DRAM output enable (active-low).
DWE#
30
O
DRAM write enable (active-low).
DB[15:0]
31:33, 36:42, 45:50
I/O
DRAM data bus.
DSCK
51
O
Output clock to DRAM.
DQM
54
O
Data input/output mask.
LA[21:0]
55:60, 63:69, 72:77,
80:82
O
RISC port address bus.
LCS[3:0]#
83:85, 88
O
RISC port chip select (active-low).
LWRLL#
89
O
RISC port low-byte write enable (active-low).
LOE#
90
O
RISC port output enable (active-low).
LD[7:0]
91:94, 97:100
I/O
RISC port data bus; (5V tolerant input).
RSD
101
I
Audio receive serial data; (5V tolerant input).
RBCK
102
I
Audio receive bit clock; (5V tolerant input).
RWS
103
I
Audio receive frame sync; (5V tolerant input).
VD33_PL
104
P
Power for PLL blocks.
VS33_PL
105
G
Ground for PLL blocks.
VREF
106
I
Internal voltage reference to video DAC.
YUV1
O
YUV pixel 1 output data.
COMP
107
I
Compensation input.
YUV3
O
YUV pixel 3 output data.
Table 1 ES6629 Pin Description
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DV-SP302
IC BLOCK DIAGRAM/ TERMINAL DESCRIPTION
IC10 : ES6629 VIDEO PROCESSOR-(3)
RSET
108
I
DAC current adjustment resistor input.
YUV4
O
YUV pixel 4 output data.
FDAC
109
O
Video DAC output. Refer to description and matrix for UDAC pin 115.
YUV7
O
YUV pixel 7 output data.
VDAC
110
O
Video DAC output. Refer to description and matrix for UDAC pin 115.
YUV6
O
YUV pixel 6 output data.
VD33_DA
111
P
Power for I/O power supply for VDAC.
VS33_DA
112
G
Ground for I/O power supply for VDAC.
YDAC
113
O
Video DAC output. Refer to description and matrix for UDAC pin 115.
YUV5
O
YUV pixel 5 output data.
CDAC
114
O
Video DAC output. Refer to description and matrix for UDAC pin 115.
YUV2
O
YUV pixel 2 output data.
UDAC
115
O
Video DAC output.
F: CVBS/chroma signal for simultaneous mode.
Y: Luma component for YUV and Y/C processing.
C: Chrominance signal for Y/C processing.
U: Chrominance component signal for YUV mode.
V: Chrominance component signal for YUV mode.
YUV0
O
YUV pixel 0 output data.
Table 1 ES6629 Pin Description (Continued)
Names
Pin Numbers
I/O
Definitions
Pin
109
110
113
114
115
Value
F DAC
V DAC
Y DAC
C DAC
U DAC
0
CVBS/Chroma
CVBS1
Y
C
N/A
1
CVBS/Chroma
CVBS1
Y
C
CVBS2
2
CVBS/Chroma
N/A
Y
C
N/A
3
CVBS/Chroma
CVBS1
N/A
N/A
CVBS2
4
CVBS/Chroma
CVBS1
N/A
N/A
N/A
5
CVBS/Chroma
CVBS1
Y
Pb
Pr
6
CVBS/Chroma
N/A
Y
Pb
Pr
7
N/A
SYNC
G
B
R
8
CVBS/Chroma
Chroma
Y
Pb
Pr
9
CVBS
CVBS1
G
B
R
10
CVBS
CVBS1
G
R
B
11
N/A
SYNC
G
R
B
12
CVBS/Chroma
N/A
Y
Pr
Pb
13
CVBS/Chroma
CVBS1
Y
Pr
Pb
14
Chroma
Y
G
R
B
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DV-SP302
IC BLOCK DIAGRAM/ TERMINAL DESCRIPTION
IC10 : ES6629 VIDEO PROCESSOR-(4)
TWS
116
O
Audio transmit frame sync output.
SEL_PLL2
I
System and DSCK output clock frequency selection is made at the rising edge of
RESET#. The matrix below lists the available clock frequencies and their
respective PLL bit settings. Strapped to VCC or ground via 4.7-k resistor; read-
only during reset.
TSD0
117
O
Audio transmit serial data port 0.
SEL_PLL0
I
Refer to the description and matrix for SEL_PLL2 pin 116.
TSD1
118
O
Audio transmit serial data port 1.
SEL_PLL1
I
Refer to the description and matrix for SEL_PLL2 pin 116.
TSD[2:3]
120, 121
O
Audio transmit serial data ports 2 and 3.
MCLK
122
I/O
Audio master clock for audio DAC.
TBCK
123
O
Audio transmit bit clock.
SPD_DOBM
124
O
S/PDIF output.
SEL_PLL3
I
Clock source select. Strapped to VCC or ground via 4.7-k resistor; read only
during reset.
SPDIF_IN
125
I
S/PDIF input; (5V tolerant input).
WBLCLK
128
O
DVD-RAM wobble detector circuit clock source to preamp.
WBL
129
O
DVD-RAM wobble output.
LG
130
O
DVD-RAM land/groove flag.
IP2
131
I
DVD-RAM header position index 2.
IP1
132
I
DVD-RAM header position index 1.
FLAG[3:0]
133:136
O
To monitor servo status.
TEXI
139
I
High-speed tracking error input.
TESTAD
140
I
Test AD input.
SBAD
141
I
Sub-beam addition input signal.
FEI
142
I
Focus input error signal.
Table 1 ES6629 Pin Description (Continued)
Names
Pin Numbers
I/O
Definitions
SEL_PLL2
SEL_PLL1
SEL_PLL0
Clock Type (MHz)
0
0
0
CLK
.5
0
0
1
CLK 5.0
0
1
0
Bypass
0
1
1
CLK 4.0
1
0
0
CLK
4.25
1
0
1
CLK
4.75
1
1
0
CLK 5.5
1
1
1
CLK 6.0
SEL_PLL3
Clock Source
0
Crystal oscillator
1
CLK input
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DV-SP302
IC BLOCK DIAGRAM/ TERMINAL DESCRIPTION
IC10 : ES6629 VIDEO PROCESSOR-(5)
TWS
116
O
Audio transmit frame sync output.
SEL_PLL2
I
System and DSCK output clock frequency selection is made at the rising edge of
RESET#. The matrix below lists the available clock frequencies and their
respective PLL bit settings. Strapped to VCC or ground via 4.7-k resistor; read-
only during reset.
TSD0
117
O
Audio transmit serial data port 0.
SEL_PLL0
I
Refer to the description and matrix for SEL_PLL2 pin 116.
TSD1
118
O
Audio transmit serial data port 1.
SEL_PLL1
I
Refer to the description and matrix for SEL_PLL2 pin 116.
TSD[2:3]
120, 121
O
Audio transmit serial data ports 2 and 3.
MCLK
122
I/O
Audio master clock for audio DAC.
TBCK
123
O
Audio transmit bit clock.
SPD_DOBM
124
O
S/PDIF output.
SEL_PLL3
I
Clock source select. Strapped to VCC or ground via 4.7-k resistor; read only
during reset.
SPDIF_IN
125
I
S/PDIF input; (5V tolerant input).
WBLCLK
128
O
DVD-RAM wobble detector circuit clock source to preamp.
WBL
129
O
DVD-RAM wobble output.
LG
130
O
DVD-RAM land/groove flag.
IP2
131
I
DVD-RAM header position index 2.
IP1
132
I
DVD-RAM header position index 1.
FLAG[3:0]
133:136
O
To monitor servo status.
TEXI
139
I
High-speed tracking error input.
TESTAD
140
I
Test AD input.
SBAD
141
I
Sub-beam addition input signal.
FEI
142
I
Focus input error signal.
Table 1 ES6629 Pin Description (Continued)
Names
Pin Numbers
I/O
Definitions
SEL_PLL2
SEL_PLL1
SEL_PLL0
Clock Type (MHz)
0
0
0
CLK
.5
0
0
1
CLK 5.0
0
1
0
Bypass
0
1
1
CLK 4.0
1
0
0
CLK
4.25
1
0
1
CLK
4.75
1
1
0
CLK 5.5
1
1
1
CLK 6.0
SEL_PLL3
Clock Source
0
Crystal oscillator
1
CLK input
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DV-SP302
IC BLOCK DIAGRAM/ TERMINAL DESCRIPTION
IC10 : ES6629 VIDEO PROCESSOR-(6)
AVSS_AD
143
G
Analog ground for ADC block.
CEI
144
I
Center error input signal.
TEI
145
I
Tracking error input signal.
RFRP
146
I
RF ripple/envelope input signal.
AVDD3_AD
147
P
Analog power supply for ADC block.
VREF21
148
O
2.1V reference voltage.
VREF09
149
O
0.9V reference voltage.
VREF15
150
O
1.5V reference voltage.
IREF
151
I
Servo data PLL interface reference current generator. Connect a resistor
between this pin and ground to set reference current.
AVDD3_DS
152
P
Analog power supply for data slicer block.
IPIN
153
I
Inverting input of data slicer.
RFIN
154
I
Analog RF signal input after passing through equalizer (minus).
RFIP
155
I
Analog RF signal input after passing through equalizer (plus).
DSSLV
156
O
Data slicer level output.
AVSS_DS
157
G
Analog ground for data slicer block.
AVSS_PL
158
G
Analog ground for data PLL block.
PDOFTR1
159
O
Servo data PLL phase detector filter pin number 1.
FDO
160
O
Servo data PLL output node of frequency detector charge pump.
FTROPI
161
I
Servo data PLL input node of loop filter OP circuit.
AVDD3_PL
162
P
Analog power supply for data PLL block.
PLLFTR1
163
I
Servo data PLL loop filter pin number 1.
PLLFTR2
164
I
Servo data PLL loop filter pin number 2.
VREF0
165
O
Servo data PLL reference voltage output.
AWRC
166
I/O
Auto wide range control VCO signal from/to AWRC DAC.
AVSS_DA
167
G
Analog ground for DAC part.
RFRPCTR
168
I/O
Central level of RFRP.
TRAY
169
O
Output voltage level for tray buffer IC.
AVDD3_DA
170
P
Analog power supply for DAC part.
SPINDLE
171
O
Output voltage level for spindle buffer IC.
FOCUS
172
O
Output voltage level for focus buffer IC.
SLEGP
173
O
Output voltage level for Sledge buffer IC (plus).
SLEGN
174
O
Output voltage level for Sledge buffer IC (minus).
TRACK
175
O
Output voltage level for tracking buffer IC.
TESTDA
176
O
Test DA output.
FGIN
177
I
Spindle hall sensor input.
Table 1 ES6629 Pin Description (Continued)
Names
Pin Numbers
I/O
Definitions
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DV-SP302
IC BLOCK DIAGRAM/ TERMINAL DESCRIPTION
IC10 : ES6629 VIDEO PROCESSOR-(7)
PHOI
178
I
Sledge photo interrupt signal input.
SCSJ
179
O
Chip selection signal to RF chip (serial data enable).
SDATA
180
I/O
Data signal from/to RF chip.
SCLK
181
O
Serial clock source to RF chip.
DFCT
182
I
Defect flag input signal.
LDC
183
O
Laser diode on/off control output.
SPDON
184
O
Spindle power driver on/off control output.
GPIO[9:4]
187:192
I/O
General-purpose input/output used for servo control; (5V tolerant input).
EAUX[3:0]
193:196
I/O
Extended auxilliary ports; (5V tolerant input).
I2CDATA
199
I/O
I2C data I/O; (5V tolerant input).
AUX0
I/O
Auxiliary port (open collector); (5V tolerant input).
I2C_CLK
200
I/O
I2C clock I/O; (5V tolerant input).
AUX1
I/O
Auxiliary port (open collector); (5V tolerant input).
IOW#
201
O
I/O Write strobe (LCS1) (active-low).
HSYNC#
I/O
Horizontal sync (active-low); (5V tolerant input).
AUX2
I/O
Auxiliary port; (5V tolerant input).
IOR#
202
O
I/O Read strobe (LCS1) (active-low).
VSYNC#
I/O
Vertical sync (active-low); (5V tolerant input).
AUX3
I/O
Auxiliary port; (5V tolerant input).
C2PO
203
I
Error correction flag from CD; (5V tolerant input).
AUX4
I/O
Auxiliary port; (5V tolerant input).
AUX[6:5]
204, 205
I/O
Auxiliary ports; (5V tolerant input).
IR
206
I
Infrared remote control input; (5V tolerant input).
AUX7
I/O
Auxiliary port; (5V tolerant input).
RESET#
207
I
Reset input (active-low); (5V tolerant input).
Table 1 ES6629 Pin Description (Continued)
Names
Pin Numbers
I/O
Definitions
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SV-SP302
IC BLOCK DIAGRAM/ TERMINAL DESCRIPTION
IC10 : ES6629 VIDEO PROCESSOR-(8)
ES6629
8/16-MB
DRAM
RF Amp
VFD Driver
Audio DAC
TV Display
Speakers
Video
EEPROM
A/V Receiver
Vibratto-II
VFD Panel
Audio ADC
Microphone In
S/PDIF
ROM/Flash
Motor Driver
OPU
Motor
DVD/CD
IR Remote
ES6603
SYSTEM BLOCK DIAGRAM
A sampling system block diagram for the ES6629 Vibratto-II DVD
player board design is shown in Figure 2.
Figure 2 ES6629 Vibratto-II System Block Diagram
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DV-SP302
IC BLOCK DIAGRAM/ TERMINAL DESCRIPTION
IC9 : HY57V641620HG D RAM-(1)
PIN CONFIGURATION
PIN DESCRIPTION
P I N
P I N N A M E
D E S C R I P T I O N
C L K
C l o c k
T h e s y s t e m c l o c k i n p u t . A l l o t h e r i n p u t s a r e r e g i s t e r e d t o t h e S D R A M o n t h e
r i s i n g e d g e o f C L K
C K E
C l o c k E n a b l e
C o n t r o l s i n t e r n a l c l o c k s i g n a l a n d w h e n d e a c t i v a t e d , t h e S D R A M w i l l b e o n e
o f t h e s t a t e s a m o n g p o w e r d o w n , s u s p e n d o r s e l f r e f r e s h
C S
C h i p S e l e c t
E n a b l e s o r d i s a b l e s a l l i n p u t s e x c e p t C L K , C K E a n d D Q M
B A 0 , B A 1
B a n k A d d r e s s
S e l e c t s b a n k t o b e a c t i v a t e d d u r i n g R A S activity
S e l e c t s b a n k t o b e r e a d / w r i t t e n d u r i n g C A S activity
A 0 ~ A 1 1
A d d r e s s
R o w A d d r e s s : R A 0 ~ R A 1 1 , C o l u m n A d d r e s s : C A 0 ~ C A 7
A u t o - p r e c h a r g e f l a g : A 1 0
R A S , C A S, W E
R o w A d d r e s s S t r o b e ,
C o l u m n A d d r e s s S t r o b e ,
W r i t e E n a b l e
R A S , C A S a n d W E d e f i n e t h e o p e r a t i o n
Refer function truth table for details
L D Q M , U D Q M
D a t a I n p u t / O u t p u t M a s k
C o n t r o l s o u t p u t b u f f e r s i n r e a d m o d e a n d m a s k s i n p u t d a t a i n w r i t e m o d e
D Q 0 ~ D Q 1 5
D a t a I n p u t / O u t p u t
M u l t i p l e x e d d a t a i n p u t / o u t p u t p i n
V DD /V S S
P o w e r S u p p l y / G r o u n d
P o w e r s u p p l y f o r i n t e r n a l c i r c u i t s a n d i n p u t b u f f e r s
V D D Q /V S S Q
D a t a O u t p u t P o w e r / G r o u n d
P o w e r s u p p l y f o r o u t p u t b u f f e r s
N C
N o C o n n e c t i o n
N o c o n n e c t i o n
V SS
D Q 1 5
V SSQ
D Q 1 4
D Q 1 3
V DDQ
D Q 1 2
D Q 1 1
V SSQ
D Q 1 0
DQ9
V DDQ
DQ8
V SS
N C
UDQM
CLK
CKE
N C
A11
A 9
A 8
A 7
A 6
A 5
A 4
V SS
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
2 5
2 6
2 7
5 4
5 3
5 2
5 1
5 0
4 9
4 8
4 7
4 6
4 5
4 4
4 3
4 2
4 1
4 0
3 9
3 8
3 7
3 6
3 5
3 4
3 3
3 2
3 1
3 0
2 9
2 8
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
L D Q M
/ W E
/CAS
/RAS
/ C S
BA0
BA1
A10/AP
A 0
A 1
A 2
A 3
VDD
54pin TSOP II
400mil x 875mil
0.8mm pin pitch
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DV-SP302
IC BLOCK DIAGRAM/ TERMINAL DESCRIPTION
IC9 : HY57V641620HG D RAM-(2)
X decoders
State Machine
A 0
A 1
A 1 1
B A 0
B A 1
Address buffers
A d d r e s s
R e g i s t e r s
M o d e R e g i s t e r s
R o w
Pre
D e c o d e r s
C o l u m n
Pre
D e c o d e r s
C o l u m n A d d
C o u n t e r
R o w a c t i v e
C o l u m n
A c t i v e
B u r s t
C o u n t e r
D a t a O u t C o n t r o l
C A S L a t e n c y
I n t e r n a l R o w
c o u n t e r
DQ0
DQ1
DQ14
DQ15
r e f r e s h
S e l f r e f r e s h l o g i c
& timer
P i p e L i n e C o n t r o l
I/O Buffer & Logic
B a n k S e l e c t
Sense AMP & I/O Gate
CLK
C K E
C S
R A S
C A S
W E
U D Q M
L D Q M
1Mx16 Bank 3
X decoders
X decoders
M e m o r y
Cell
A r r a y
Y d e c o d e r s
X decoders
1Mx16 Bank 0
1Mx16 Bank 1
1Mx16 Bank 2
FUNCTIONAL BLOCK DIAGRAM
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DV-SP302
IC BLOCK DIAGRAM/ TERMINAL DESCRIPTION
IC8 : M24C02WMN6 EEPROM
E0, E1, E2
Chip Enable Inputs
SDA
Serial Data/Address Input/
Output
SCL
Serial Clock
WC
Write Control
VCC
Supply Voltage
VSS
Ground
3
E0-E2
SDA
VCC
M24Cxx
WC
SCL
VSS
1
2
3
4
8
7
6
5
SDA
VSS
SCL
WC
E1
E0
VCC
E2
M24Cxx
M24Cxx - W
M24Cxx - R
Logic Diagram
Signal Names
SO Connections
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LOgic Diagram
Signal Names
DV-SP302
TSOP Connections
IC BLOCK DIAGRAM/ TERMINAL DESCRIPTION
IC12 : M29W800DT MEMORY FLASH
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1
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PIN CONNECTIONS
PIN DESCRIPTION
DV-SP302
IC BLOCK DIAGRAM/ TERMINAL DESCRIPTION
IC81 : M74HCU04 INVERTER IC
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2
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TEL 13942296513
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2
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2
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8
0
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1
5
1
3
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3
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DV-SP302
IC BLOCK DIAGRAM/ TERMINAL DESCRIPTION
IC14 : MM1507 VIDEO SWITCH
Measuring circuit
Block Diagram
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DV-SP302
GND
GND
VOUTR
VOUTR
CAP
CAP
NC
NC
BCKIN
BCKIN
LRCIN
LRCIN
DIN
DIN
10
10
9
8
14
14
13
13
12
12
11
11
WM8761
WM8761
5
6
7
1
2
3
4
VDD
VDD
VOUTL
VOUTL
MUTE
MUTE
NC
NC
DEEMPH
DEEMPH
MCLK
MCLK
FORMAT
FORMAT
BCKIN
IN
AUD
UDIO
IO
INTERFACE
CE
MUTE
TE
CONTROL
OL
INTERFACE
CE
VOUTL
TL
VOUTR
TR
SIGMA
MA
DELTA
TA
MODULATOR
OR
LRC
RCIN
IN
DIN
IN
MUTE
TE
SIGMA
MA
DELTA
TA
MODULATOR
OR
DIGI
GITAL F
FILTERS
RS
MCLK
DEEMPH
MUTE
FORMAT
LOW
OW
PA
PASS
SS
FILTER
ER
LOW
OW
PASS
PASS
FILTER
ER
CAP
AP
DAC
AC
DAC
AC
GND
VDD
WM8761
61
PIN DESCRIPTION
PIN
NAME
TYPE
DESCRIPTION
1
LRCIN
Digital input
Sample rate clock input
2
DIN
Digital input
Serial audio data input
3
BCKIN
Digital input
Bit clock input
4
NC
No connect
No internal connection
5
CAP
Analogue output
Analogue internal reference
6
VOUTR
Analogue output
Right channel DAC output
7
GND
Supply
Negative supply
8
VDD
Supply
Positive supply
9
VOUTL
Analogue output
Left channel DAC output
10
MUTE
Digital input
Soft mute control, Internal pull down
High Impedance = Automute
High = Mute ON
Low = Mute OFF
11
NC
No connect
No internal connection
12
DEEMPH
Digital input
De-emphasis select, Internal pull up
High = de-emphasis ON
Low = de-emphasis OFF
13
FORMAT
Digital input
Data input format select, Internal pull up
Low = 24-bit right justified or DSP ‘late’
High = 16-24-bit I2S or DSP ‘early’
14
MCLK
Digital input
Master clock input
BLOCK DIAGRAM
PIN CONFIGURATION
IC BLOCK DIAGRAM/ TERMINAL DESCRIPTION
IC15 : WM8761 D/D Converter
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9
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TEL 13942296513
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2
9
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1
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7
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DV-SP302
FL TUBE VIEW
FL91 : HNV-12SM69T
ANODE CONNECTION
GRID ASSIGNMENT
INTRO
INTRO
REPEAT
REPEAT
1 ALLA-B
1 ALLA-B
RESUME
RESUME
RANDOM
RANDOM
SEC
SEC
MEM.
MEM.
MIN
MIN
HOUR
HOUR
TRACK
TRACK
CHAPTER
CHAPTER
TITLE
TITLE
PBC
PBC
PROGRESSIVE
PROGRESSIVE
DVD
DVD
VCD
VCD
CD
CD
MP3
MP3
COL
S1
S1
COL
g
f
e
r
p
n
c
d
m
a
h
j
k
b
(2G - 11G)
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DV-SP302
IC BLOCK DIAGRAM/ TERMINAL DESCRIPTION
IC91 : uPD16311 FL Driver-(1)
PIN CONFIGURATION
SW1
SW2
SW3
SW4
DOUT
DIN
IC
CLK
STB
KEY1
KEY2
KEY3
KEY4
1
2
3
4
5
6
7
8
9
10
11
12
13
39
38
37
36
35
34
33
32
31
30
29
28
27
14
15
16
17
18
19
20
21
22
23
24
25
26
52
51
50
49
48
47
46
45
44
43
42
41
40
VDD
Seg1/KS1
Seg2/KS2
Seg3/KS3
Seg4/KS4
Seg5/KS5
Seg6/KS6
Seg7/KS7
Seg8/KS8
Seg9/KS9
Seg10/KS10
Seg11/KS11
Seg12/KS12
Grid6
Grid7
Grid8
Seg20/Grid9
Seg19/Grid10
VEE
VDD
Seg18/Grid11
Seg17/Grid12
Seg16/Grid13
Seg15/Grid14
Seg14/Grid15
Seg13/Grid16
OSD
VSS
LED1
LED2
LED3
LED4
LED5
VDD
Grid1
Grid2
Grid3
Grid4
Grid5
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DV-SP302
IC BLOCK DIAGRAM/ TERMINAL DESCRIPTION
IC91 : uPD16311 FL Driver-(2)
Serial I/F
OSD
Command decoder
Display memory
20 bit x 16 word
Timming generator
key scan
4-bit latch
5-bit latch
16-bit shift register
Dimming
circuit
20-bit output latch
Data selector
Segment driver
Segment/ grid
driver
Grid driver
Key data memory (4 x 12)
R
VDD
4
4
20
12
8
8
8
16
8
VDD
VSS
VEE
(+5V)
(-30V)
(0V)
LED1
LED6
DIN
DOUT
CLK
STB
Key1
to
Key4
SW1
to
SW4
Seg1
Seg12
Seg13/Grid16
Seg20/Grid9
Grid1
Grid8
BLOCK DIAGRAM
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DV-SP302
IC BLOCK DIAGRAM/ TERMINAL DESCRIPTION
IC91 : uPD16311 FL Driver-(3)
PIN FUNCTION
Pin No.
Symbol
Pin name
Description
DIN
DOUT
STB
CLK
OSD
Seg1/KS1 to
Seg12/KS12
Grid1 to Grid6
Seg13/Grid16 to
Seg20/Grid9
LED1 to LED6
Key1 to Key4
SW1 to SW4
VDD
VSS
VEE
IC
Data input
Inputs serial data at rising edge of shift clock,
starting from lower bit.
Outputs serial data at falling edge of shift clock, starting from
lower bit. This is N-ch open-drain output pin.
Initializes serial interface at rising or falling edge to make
uPD16311 waiting for reception of command. Data input
after STB has fallen is processed as command. While command
data is processed, current processing is stopped, and serial interface
is initializes. While STB is high, CLK is ignored.
Reads serial data at rising edge, and outputs data at falling edge.
Connect resistor for determining oscillation frequency to this pin.
Segment output pins (Dual function as key source).
Grid output pins.
Tease pins are selectable for segment or grid output.
CMOS output. +20 mA max..
Data input to these pins is latched at end of display cycle.
These pins constitute 4-bit general-purpose input port.
5 V = 10 %
connect this pin to GND of system.
VDD - 35 V max.
Be sure to leave this pin open (this pin is at VDD level).
Data output
Strobe
Clock input
Oscillator pin
High-voltage output
(segment)
High-voltage output (Grid)
High-voltage output
(segment/ grid)
LED output
Key data input
switch input
Logic power
Logic ground
Pull-down level
Internally connection
6
5
9
8
52
15 to 26
44 to 37
27 to 32
35 to 36
50 to 46
10 to 13
1 to 4
14, 33, 45
51
34
7
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DV-SP302
UPGRADE FIRM WARE
Confirm the version of firmware.
1. Open a tray.
2. Press the "SEARCH DOWN" button 2 second at the unit and
"POWER" key on the remote controller.
Displayed on the FL tube like "1022". ex) 1022= FW version 1.22
3. Turn off the power switch and power on, again.
Upgrade the firmware
1. Connect a video monitor to video out jack on the DV-SP302.
2. Turn on the power switch and standby switch on.
3. Setting the disc on the tray. (Down load firmware data disc)
4. Will start the Firm Ware updating.
Display repeat "ERASES" and "WRITE" on the monitor.
Will tray open after finish the updating.
Light up "STANDBY/ON" LED. = Complete the upgrade FW.
5. Turn off mechanical power switch.
6. Turn on the power switch again and take out the disc and close the tray.
Initializing
4. While display version of firmware, turn off a mechanical power switch.
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NOTE
Pack the unit that have been set the DVD mechanism
to initial mode (Push standby button so that set can
goes into standby mode. Pull out AC-cord (after
check power switch ON).
STEP 1 : LABEL FOR SET POSITION
DETAIL - CARD CERTIFICATE
Rear side
Front side
Apply to DV-SP302 CUR6P only
Record trier's name and data
before packing in card certificate.
Rear side
Changed packing location
For Rear panel
For Carton box
STEP 2 : KNOB POWER POSITION
STEP 3 : SET PACKING
3
Rear side
Bottom side
Rear side
Bottom side
STEP 4
1
Stick in the card certificate
23
4
Fron
8
Stick in the middle position
on the front side wall
by double side tape
STEP
Front side
OFF (NG)
ON
OFF
POWER
ON (OK)
Knob power position : ON
Label Rating
Only DV-SP302(G) CUK3P
21
2
Rear panel
POS Label
PACKING PROCESURE
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4 : SET IN BOX
6
7
5
ont side
P 5 : AC CORD POSITION
10
Stick in the accessory
Left side
11
STEP 6 : PACKING IN ACCESSORIES
(PUT ON THE POLY BAG).
Attach tape to PE bag.
Battery
Detail view
20
12
13
14
15
16
17
Front side
11
Roll a PE bag and
attach tape to PE bag. (2 place)
19
18
Not apply to DV-SP302 CUR6P (CHINA VERSION ONLY)
Stick in the accessory
STEP 7 : LABEL FOR BOX POSITION
For Rear panel
Right side
Front
DV-SP302
DV-SP302
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TEL 13942296513 QQ 376315150 892498299
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NOTE
Pack the unit that have been set the DVD mechanism
to initial mode (Push standby button so that set can
goes into standby mode. Pull out AC-cord (after
check power switch ON).
STEP 1 : LABEL FOR SET POSITION
DETAIL - CARD CERTIFICATE
Rear side
Front side
Apply to DV-SP302 CUR6P only
Record trier's name and data
before packing in card certificate.
Rear side
Changed packing location
For Rear panel
For Carton box
STEP 2 : KNOB POWER POSITION
STEP 3 : SET PACKING
3
Rear side
Bottom side
Rear side
Bottom side
STEP 4 : SET IN BOX
1
Stick in the card certificate
23
4
6
7
5
Front side
8
Stick in the middle position
on the front side wall
by double side tape
STEP 5 : AC CORD POSITION
10
Front side
Stick in the accessory
Left side
11
STEP 6 : PACKING IN ACCESSORIES
(PUT ON THE POLY BAG).
Attach tape to PE bag.
Battery
Detail view
20
12
13
14
15
16
17
Front side
11
Roll a PE bag and
attach tape to PE bag. (2 place)
19
18
Not apply to DV-SP302 CUR6P (CHINA VERSION ONLY)
Stick in the accessory
STEP 7 : LABEL FOR BOX POSITION
For Rear panel
Right side
Front
DV-SP302
OFF (NG)
ON
OFF
POWER
ON (OK)
Knob power position : ON
Label Rating
Only DV-SP302(G) CUK3P
21
2
Rear panel
POS Label
DV-SP302
PACKING PROCESURE
w w w
.
x i a o y u 1 6 3 .
c o m
Q Q
3 7 6 3 1 5 1 5 0
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T E L
1 3 9 4 2 2 9 6 5 1 3
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PARTS LIST
PACKING PARTS LIST
NO. PART NO. PART NAME
DESTINATION
DESCRIPTION
(B)CDD1N (S)CDD1N (B)CUA4P (S)CUA4P (G)CUT3P (G)CUK3P (G)CUR6P
55832660
POS Label
AC PRI LABEL POS DV-SP302(B) CDD1N
1
55932730
POS Label
AC PRI LABEL POS DV-SP302(S) CDD1N
1
55932750
POS Label
AC PRI LABEL POS DV-SP302(B) CUA4P
1
55932760
POS Label
AC PRI LABEL POS DV-SP302(S) CUA4P
1
55932740
POS Label
AC CARTON DV-SP302(S) CDD1N DW-2
1
5593266A Carton box
AC CARTON DV-SP302(B) CUA4P DW-2
1
5593267A Carton box
AC CARTON DV-SP302(S) CUA4P DW-2
1
5593268A Carton box
AC EMBD IMA FRONT BD DV-SP302(S) CDD1N
1.0
55931400
Front display board
AC EMBD IMA FRONT BD DV-SP302(S) CUA4P
1.0
55931410
Front display board
1.0
55931400-1 FL tube board
1.0
55931410-1 FL tube board
1.0
55931400-2 Key switch board
1.0
55931410-2 Key switch board
1.0
55931400-3 Standby switch board
1.0
55931410-3 Standby switch board
1.0
55931400-4 Remote sensor board
1.0
55931410-4 Remote sensor board
AC EMBD IMA MAIN BD DV-SP302(S) CDD1N
1.0
55931680
DVD Main board assy
AC EMBD IMA MAIN BD DV-SP302(B) CUA4P
1.0
55931700
DVD Main board assy
AC EMBD IMA MAIN BD DV-SP302(S) CUA4P
1.0
55931710
DVD Main board assy
AC EMBD IMA OUT BD DV-SP302(S) CDD1N
1.0
55931920
Output terminal board assy
AC EMBD IMA OUT BD DV-SP302(B) CUA4P
1.0
55931940
Output terminal board assy
AC EMBD IMA OUT BD DV-SP302(S) CUA4P
1.0
55931950
Output terminal board assy
AC DEC BUTTON STANDBY DV-SP301(S) UDD1N HIPS
1.0
1.0
55688540
Button Standby
AC DEC CABINET PANEL FRONT DV-SP302(S) CDD1N
1.0
55932570
Front panel
AC DEC CABINET PANEL FRONT DV-SP302(B) CUA4P
1.0
55932580
Front panel
AC DEC CABINET PANEL FRONT DV-SP302(S) CUA4P
1.0
55932590
Front panel
AC DEC DOOR TRAY DV-SP302(S) CDD1N SI01TH
1.0
1.0
55932610
Door
AC DEC BUTTON 6KEY DV-SP301(S) UDD1N HIPS
1.0
1.0
55688560
Button 6 key
AC DEC BUTTON OPEN/CLOSE DV-SP301(S) UDD1N HIPS
1.0
1.0
55688520
Button Open/ Close
AC DEC KNOB POWER DV-SP301(S) UDD1N
1.0
1.0
55688420
Knob
AC PUN COVER TOP DV-SP301(S) UDD1N PCM 0.7T SI01TH
1.0
1.0
55688590
Top cover
: Silver color model
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