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'BASIC DVD MECHANISM : LDM-H109
(6721R-0300A)
DVD PLAYER
XD-DV290
S/M Code No. 09-99C-337-5R1
U(B)
SERVICE MANUAL
REVISION
DATA
This Service Manual is the “Revision Publishing” and replaces “Simple Manual”
(S/M Code No.09-99C-337-5T1).
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TABLE OF CONTENTS
SPECIFICATIONS .................................................................................................................................. 3
ACCESSORIES/PACKAGE LIST ........................................................................................................... 3
PROTECTION OF EYES FROM LASER BEAM DURING SERVICING/
Precaution to replace Optical block......................................................................................................... 4
DISASSEMBLY INSTRUCTIONS ...................................................................................................... 5-10
ELECTRICAL MAIN PARTS LIST ........................................................................................................ 11
TRANSISTOR ILLUSTRATION ............................................................................................................ 12
BLOCK DIAGRAM-1 (OVERALL) ......................................................................................................... 13
BLOCK DIAGRAM-2 (POWER) ............................................................................................................ 14
BLOCK DIAGRAM-3 (RF/DSP/SERVO) ............................................................................................... 15
BLOCK DIAGRAM-4 (AUDIO) .............................................................................................................. 16
BLOCK DIAGRAM-5 (MPEG) ............................................................................................................... 17
BLOCK DIAGRAM-6 (SYSTEM CONTROL) ........................................................................................ 18
WIRING-1 (MAIN: COMPONENT SIDE) ........................................................................................ 19, 20
WIRING-2 (MAIN: CONDUCTOR SIDE) ........................................................................................ 21, 22
SCHEMATIC DIAGRAM-1 (MAIN 1/5)............................................................................................ 23, 24
SCHEMATIC DIAGRAM-2 (MAIN 2/5)............................................................................................ 25, 26
SCHEMATIC DIAGRAM-3 (MAIN 3/5)............................................................................................ 27, 28
SCHEMATIC DIAGRAM-4 (MAIN 4/5)............................................................................................ 29, 30
SCHEMATIC DIAGRAM-5 (MAIN 5/5)............................................................................................ 31, 32
SCHEMATIC DIAGRAM-6 (JACK) ................................................................................................. 33, 34
WIRING-3 (JUNCTION/JACK) ........................................................................................................ 35, 36
SCHEMATIC DIAGRAM-7 (JUNCTION) ........................................................................................ 37, 38
WIRING-4 (TIMER/KEY/POWER) .................................................................................................. 39, 40
SCHEMATIC DIAGRAM-8 (TIMER/KEY) ....................................................................................... 41, 42
SCHEMATIC DIAGRAM-9 (POWER) ............................................................................................. 43, 44
WAVE FORM ................................................................................................................................... 45-47
TROUBLE-SHOOTING .................................................................................................................... 48-57
LCD DISPLAY ....................................................................................................................................... 58
IC DESCRIPTION ............................................................................................................................ 59-77
IC BLOCK DIAGRAM....................................................................................................................... 78-80
MECHANICAL EXPLODED VIEW 1/1 .................................................................................................. 81
MECHANICAL PARTS LIST 1/1 ........................................................................................................... 82
MECHANISM EXPLODED VIEW 1/1 ............................................................................................. 83, 84
MECHANISM PARTS LIST 1/1............................................................................................................. 85
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SPECIFICATIONS
DVD PLAYER
Power supply
120 V, 60 Hz
Power consumption
20 W
Weight
3.5 kg (7.7 lbs)
External dimensions
430 * 91 * 293 (W * H * D)
Signal system
NTSC
Laser
Semiconductor laser, wavelength 650 nm
Frequency range (digital audio)
2 Hz to 44 kHz
Signal-to-noise ratio (digital audio)
More than 105 dB (EIAJ)
Audio dynamic range (digital audio)
More than 95 dB (EIAJ)
Harmonic distortion (digital audio)
0.003%
Wow and flutter
Below measurable level (less than +0.001% (W.PEAK)) (EIAJ)
Operating conditions
Temperature : 41˚F to 95˚F,
Operation status : Horizontal
OUTPUTS
Video outputs
1.0 V (p-p), 75 Ω, negative sync., RCA jack * 1
S video outputs
(Y) 1.0 V (p-p), 75 Ω, negative sync.,Mini DIN 4-pin * 1
(C) 0.286 V (p-p), 75 Ω
Component video output
(Y) 1.0 V (p-p), 75 Ω, negative sync., RCA jack * 1
(Pb)/ (Pr) 0.7 V (p-p), 75 Ω
Audio output (digital audio)
0.5 V (p-p), 75 Ω, RCA jack * 1
Audio output (optical audio)
Optical connector * 1
Audio output (analog audio)
2.0 Vrms (1 kHz, 0 dB), 330 Ω, RCA jack (L, R) * 2
•
Design and specifications are subject to change without notice.
•
Weight and dimensions shown are approximate.
•
Dolby noise reduction manufactured under license from
Dolby Laboratories Licensing Corporation.
“DOLBY” and the double-D symbol
and “PRO LOGIC” are trademarks of Dolby Laboratories
Licensing Corporation.
Laboratories Licensing Corporation.
•
Manufactured under license from Digital Theater Systems, Inc.
US Pat. No. 5,451,942 and other worldwide patents issued and
pending. “DTS” and “DTS Digital Surround” are trademarks of
Digital Theater Systems, Inc. c 1996 Digital Theater systems,
Inc. All rights reserved.
REF. NO
PART NO.
KANRI
DESCRIPTION
NO.
ACCESSORIES/PACKAGE LIST
1 S8-35R-S00-08G INSTRUCTION BOOK DVD-2520N
2 S7-11R-2N0-13A DVD-2520 REM
3 S8-615-20G-000 DVD-2520N CABLE ASSY
4 S5-640-17B-000 PLUG ASSY 1WAY(YL)
5 S5-640-18B-000 PLUG ASSY 2WAY(RD/WH)
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PROTECTION OF EYES FROM LASER BEAM DURING SERVICING
VAROITUS!
Laiteen Käyttäminen muulla kuin tässä käyttöohjeessa mainit-
ulla tavalla saattaa altistaa käyt-täjän turvallisuusluokan 1 ylit-
tävälle näkymättömälle lasersäteilylle.
VARNING!
Om apparaten används på annat sätt än vad som specificeras i
denna bruksanvising, kan användaren utsättas för osynling
laserstrålning, som överskrider gränsen för laserklass 1.
Caution: Invisible laser radiation when
open and interlocks defeated avoid expo-
sure to beam.
Advarsel:Usynling laserståling ved åbning,
når sikkerhedsafbrydere er ude af funktion.
Undgå udsættelse for stråling.
CAUTION
Use of controls or adjustments or performance of procedures
other than those specified herein may result in hazardous
radiation exposure.
ATTENTION
L\'utilisation de commandes, réglages ou procédures autres que
ceux spécifiés peut entraîner une dangereuse exposition aux
radiations.
ADVARSEL!
Usynlig laserståling ved åbning, når sikkerhedsafbrydereer ude
af funktion. Undgå udsættelse for stråling.
This Compact Disc player is classified as a CLASS 1 LASER
product.
The CLASS 1 LASER PRODUCT label is located on the rear
exterior.
This set employs laser. Therefore, be sure to follow carefully the
instructions below when servicing.
WARNING!
WHEN SERVICING, DO NOT APPROACH THE LASER EXIT
WITH THE EYE TOO CLOSELY. IN CASE IT IS NECESSARY TO
CONFIRM LASER BEAM EMISSION. BE SURE TO OBSERVE
FROM A DISTANCE OF MORE THAN 30cm FROM THE
SURFACE OF THE OBJECTIVE LENS ON THE OPTICAL
PICK-UP BLOCK.
CLASS 1
KLASSE 1
LUOKAN 1
KLASS 1
LASER PRODUCT
LASER PRODUKT
LASER LAITE
LASER APPARAT
Precaution to replace Optical block
(LPC-512A)
1) After the connection, remove solder shown in
the right figure.
Body or clothes electrostatic potential could ruin
laser diode in the optical block. Be sure ground
body and workbench, and use care the clothes
do not touch the diode.
Solder
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DISASSEMBLY INSTRUCTIONS
CAUTION BEFORE STARTING SERVICING
Electronic parts are susceptible to static electricity and may easily damaged, so do not forget to take a proper
grounding treatment as required.
Many screws are used inside the unit. To prevent missing, dropping, etc. of the screws, always use a
magnetized screw driver in servicing. Several kinds of screws are used and some of them need special
cautions. That is, take care of the tapping screws securing molded parts and fine pitch screws used to secure
metal parts. If they are used improperly, the screw holes will be easily damaged and the parts can not be
fixed.
CABINET DISASSEMBLY
1. Top Case
1) Release 7 screws (A). (See Fig-1)
2) Lift the top case with holding the back of it, and remove
it in the direction of the arrow.
2. Tray Door
1) Eject the disc tray.
2) Lift up the tray door in the direction of the arrow.
3. Front Panel
1) Eject the disc tray. (See Fig-2)
2) Remove the tray door. (See Fig-2)
3) Release 2 screws (B).
4) Pull the front panel toward you while pressing 7
stoppers to disengage, and remove the front panel. (See
Fig-3)
Tray Door
Disc Tray
Fig-2
Fig-1
Front Panel
Stopper
Stopper
(B)
(B)
(A)
Top Case (A)
(A)
(A)
(A)
(A)
(A)
Fig-3
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CIRCUIT BOARD DISASSEMBLY
Note: Before removing the main circuit board, be sure to
shortcircuit the laserdiode output land.
After replacing the main circuit board, open the land after
inserting the flexible connector.
(Refer to Mechanism Disassembly)
4. Main/JACK C.B
1) Remove the top case. (See Fig-1)
2) Release 10 screws (C), and take out the main/JACK
C.B. (See Fig-4)
3) Remove the flexible connectors and the connector from
main circuit board.
4) Then, remove the main JACK C.B.
5. Power C.B
1) Release 4 screws (D). (See Fig-5)
Main C.B
Flexible
connector
Flexible
connector
JACK C.B
(C)
(C)
(C)
(C)
(C)
(C)
(C)
(C)
(C)
Power Code
Power C.B
(D)
(D)
(D)
(D)
Fig-4
Fig-5
6. TIMER and Key C.B
1) Remove the front panel. (See Fig-3)
2) Release 5 screws (E), and remove the TIMER C.B.
(E)
(E)
(E)
(E)
(E)
TIMER C.B
Key C.B
Fig-6
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DECK MECHANISM PARTS LOCATION
• Bottom View
• Top View
Procedure
Starting No.
5
5, 6
2
2, 8
2, 8
2, 8
2, 8, 11
2, 8, 11
2, 8, 12, 13
2, 8, 12-14
2, 8, 12-14
2, 8, 12-16
2, 8, 9
2, 8, 9
2, 8, 9
2, 8, 9-20
1, 2, 8, 9
1, 2, 8, 9
2, 8, 9
2, 8, 9
2, 8
2, 8, 26
2, 8, 26, 27
2, 8, 26-28
2, 8, 26-29
1, 2, 8, 26-30
1, 2, 8, 26-31
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Parts
Junction P.C.Board
Bracket Assembly Clamp
Bracket Clamp
Clamp Assembly Disk
Plate Clamp
Magnet Clamp
Clamp Lower
Tray Disk
Base Assembly Feed
Rubber R
Spring Skew
Shaft PU Main
Shaft PU Sub
Mechanism Assembly
PU Unit
Guide Freed PU
Spring Guide Feed
Pick up Assembly General
Motor (Mech.)
Shaft Lead Screw
Motor Assembly PU Freed
Base PU (Outsert)
Base Assembly Main
Holder Assembly Deck on
Frame Assembly Up/Down
Rubber F
Belt Loading
GearPulley
Gear Loading
Gear Emergency
Cam Loading
Motor Assembly Loading
Base Main
Fixing Type
4 Screws,
4 Locking Tabs
2 Screws
1 Locking Tab
1 Connector
1 Screw
1 Hook
1Screw
3Screws
2 Locking Tabs
1 Locking Tab
2 Locking Tabs
1 Screw
2 Screws
1 Locking Tab
Disassembly
Bottom
Bottom
Bottom
Bottom
Bottom
Figure
4-1
4-2
4-2
4-2
4-2
4-2
4-2
4-3
4-4
4-4
4-4
4-4
4-4
4-4
4-4
4-4
4-4
4-4
4-4
4-4
4-4
4-5
4-5
4-5
4-5
4-5
4-5
4-5
4-5
4-5
4-5
4-5
Note: When reassembling, perform the procedure in reverse order.
The “Bottom” on Disassembly column of above
Table indicates the part should be disassembled at the
Bottom side.
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DECK ASSEMBLY
BRACKET CLAMP
CLAMP
ASSEMBLY DISK
BRACKET CLAMP
PLATE CLAMP
(S2)
(S2)
(A)
(Fig-A)
MAGNET CLAMP
CLAMP LOWER
7. Junction C.B (Fig-7)
1) Put the Deck Assembly face down. (Bottom side)
2) Release 4 Screws (S1).
3) Unlock 4 Locking tabs (L1).
4) Lift up the Junction C.B a little to disconnect the
Connector (C1).
5) Disconnect 3 Connectors (C2, C3, C4).
DECK MECHANISM ASSEMBLY
DECK ASSEMBLY
JUNCTION
C.B
(C2)
(C1)
(C3)
(C4)
(L1)
(L1)
(L1)
(L1)
(S1)
(S1)
(S1)
(S1)
Fig-7
Fig-8
8. Bracket Assembly Clamp (Fig-8)
1) Put the Deck Assembly on original position. (Top side)
2) Release 2 Screws (S2).
3) Lift up the Bracket Assembly Clamp.
8-1.
Clamp Assembly Disk
1) Place the Clamp Assembly Disk as Fig-(A).
2) Lift up the Clamp Assembly Disk in direction of arrow
(A).
3) Separate the Clamp Assembly Disk from the Bracket
Clamp.
8-1-1.
Plate Clamp
1) Turn the Plate Clamp to counterclockwise direction and
then lift up the Plate Clamp.
8-1-2.
Magnet Clamp
8-1-3.
Clamp Lower
8-2.
Bracket Clamp
9. Tray Disk (Fig-9)
1) Insert and push a Driver in the emergency eject hole (A)
at the front side, or put the Driver on the Lever (B) of
the Gear Emergency and pull the Lever (B) in direction
of arrow (A) so that the Tray Disk is ejected about 15-
20mm.
2) Pull the Tray Disk until the moving is locked by the
Locking Tab (L2).
3) Unlock the Locking tab (L2) in direction of arrow (B).
4) Separate the Tray Disk completely.
TRAY DISK
EMERGENCY
EJECT HOLE
LEVER
BOTTOM SIDE VIEW
(A)
(B)
(L2)
(B)
(A)
Fig-9
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10. Base Assembly Feed (Fig-10)
1) Disconnect the Connector (C5)
2) Release the Screw (S3).
10-1. Rubber R
10-2. Spring Skew
1) Press the (A) position of the Spring Skew and unlock
the Spring Skew locking.
10-3. Shaft PU Main
10-4. Shaft PU SUB
Note: When reassembling, be careful not to change the
Shaft PU Main (Long) and the Shaft PU Sub (Short).
10-5. Mechanism Assembly PU Unit
10-5-1. Guide Feed PU
1) Release the Screw (S4) and separate the Guide Feed PU
from the Pick up Assembly General.
10-5-2. Spring Guide Feed
MOTOR (MECH.)
BASE PU (OUTSERT)
PICK UP
ASSEMBLY GENERAL
SHAFT LEAD SCREW
MOTOR
ASSEMBLY PU
FEED
P.C. BOARD
Fig-(A)
SPRING
GUIDE FEED
(S5)
(S5)
(L3)
(A)
(S3)
(A)
(C5)
(S4)
BLACK
RED
RUBBER R
SPRING SKEW
(L4)
(A)
SHAFT PU SUB
SHAFT PU MAIN
GUIDE FEED PU
BASE PU (OUTSERT)
CABLE FLEXIBLE
MOTOR ASSEMBLY PU FEED
Fig-10
10-5-3. Pick Up Assembly General
10-6. Motor (mech.)
1) Release the 3 Screws (S5) at bottom side.
2) Push down the Motor (Mech.) and separate from the
Base PU (Outsert).
10-7. Shaft Lead Screw
1) Push the Shaft Lead Screw in direction on arrow (A) a
little and lift up the Shaft Lead Screw.
10-8. Motor Assembly PU Feed.
1) Unlock the Locking tab (L3) and lift up the P.C.Board.
2) Unlock two Locking Tabs (L4) and push down the
Motor Assembly PU Feed.
3) Separate the Motor Assembly PU Feed from the Base
PU (Outsert).
Note: When reassembling, place the Motor Assembly PU
Feed as Fig-(A) and insert the Cable Flexible to the
Hole (A) of the Base PU (Outsert). (See Fig-(A))
10-9. Motor (mech.)
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11. Base Assembly Main (Fig-11)
11-1. Holder Assembly Deck On
1) Push the Locking tabs (L5) at bottom side of the Holder
Assembly Deck On in direction of arrow (A) and
separate to bottom side. (See Fig-(A))
11-2. Frame Assembly Up/Down.
1) Push the two Locking tabs (L6) and lift up the Frame
Assembly Up/Down.
Note: When reassembling, insert the Lever (R1) of the
Frame Assembly Up/Down to the Groove (R2) of the
Gear Emergency and lock the two Locking Tabs
(L6). (See Fig-(B))
11-3. Rubber F
11-4. Belt Loading
11-5. Gear Pulley
1) Release the Screw (S6) and lift up the Gear Pulley.
11-6. Gear Loading
11-7. Gear Emergency
Note: When reassembling, confirm that the Hole (A) of the
Cam Loading is aligned to the Hole (B) of the Gear
Emergency as Fig-(C).
For this alignment, place the Gear Emergency and
Cam Loading as Fig-(D), and then move the Gear
Emergency in direction of arrow (B) until these two
gears are aligned as Fig-(C).
11-8. Cam Loading
11-9. Motor Assembly Loading
1) Release two Screws (S7).
2) Unlock the Locking tab (L7) and separate the Motor
Assembly Loading to bottom side.
Note: When reassembling, confirm that the Connector (2
Pin) is aligned as Fig-(E)
11-10. Base Main
Fig-11
(R1)
(R2)
MOTOR ASSEMBLY LOADING
Fig-(E)
Fig-(A)
BOTTOM SIDE VIEW
BASE MAIN
HOLDER
ASSEMBLY
DECK ON
(L7)
(L6)
(R2)
(R1)
(S6)
(L6)
(L5)
(L5)
(A)
BELT LOADING
GEAR EMERGENCY
Fig-(B)
Fig-(D)
Fig-(C)
CAM LOADING
CONNECTOR(2 PIN)
GEAR LOADING
GEAR PULLY
FRAME ASSEMBLY UP/DOWN
RUBBER F
(S7)
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11
REF. NO
PART NO.
KANRI
DESCRIPTION
NO.
REF. NO
PART NO.
KANRI
DESCRIPTION
NO.
ELECTRICAL MAIN PARTS LIST
IC
SI-AM2-980-01A IC,AM29F800B-120EC
SI-AL2-402-10E IC,AT24C02N-10SC-2.7
SI-AL4-981-92B IC,AT49F8192A-90TC
SI-RH5-983-20A IC,BA5983FP-E2
SI-RH6-859-20A IC,BA6859AFP-E2
SI-RW8-610-00A IC,BT861
SI-CU6-133-03A IC,CL61330(ZIVA3)
SI-GS3-301-00C IC,GDC25D801
SI-GS7-142-60E IC,GM71C4260CJ-60
SI-GS7-216-16C IC,GM72V161621ET-7
SI-HI6-417-03B IC,HD6417034AFI20
SI-SS4-310-00A IC,KA431AZ
SI-SS7-542-00A IC,KA7542Z
SI-SS7-808-00H IC,KA78R08
SI-KE3-930-00G IC,KIA393F-EL
SI-KE4-310-00A IC,KIA431
87-001-196-010 IC,KIA7042P
SI-SS4-161-02F IC,KM4161020CT-G7
SI-SA8-661-12C IC,LC866112B-5N21
SI-JR3-414-00C IC,NJM3414AM-TE
SI-JR4-580-00B IC,NJM4580M
SI-BB1-716-00A IC,PCM1716E
SI-BB1-700-00A IC,PLL1700E
SI-SH2-050-00A IC,PQ20WZ5U
SI-SH3-130-00A IC,PQ3DZ13U
SI-TI7-437-40K IC,SN74AHC374PWLE
SI-TO1-254-00A IC,TA1254F
SI-TO7-040-00F IC,TC7W04FU
SI-MQ5-316-25A IC,V53C16256HK50
SI-XL9-536-15A IC,XC9536-15VQ44C
TRANSISTOR
ST-R10-300-9AA C-TR,KRC103S-T1
ST-R38-750-9AC C-TR,KTC3875S-GR-T1
ST-R10-370-9BB TR,2SA1037K-Q
ST-R10-500-9AD TR,KRA105M
ST-R10-300-9AE TR,KRC103M
ST-R10-500-9AB TR,KRC105M
ST-R11-510-0AA TR,KSB1151-Y
ST-R13-005-0AB TR,KSE13005F
ST-R15-040-9BF TR,KTA1504S-Y
ST-R15-050-9AD TR,KTA1505S-Y
ST-R31-980-9AC TR,KTC3198-TP-BL
ST-R44-190-0AA TR,KTC4419
ST-R13-040-9BA TR,KTD1304S
ST-R10-000-9CB TR,UMX1N TP
ST-R10-000-9BM TR,UMZ1N TL
DIODE
SD-D19-300-9AB C-DIODE,KDS193(F3)
SD-R15-402-0BA DIODE,1N5402
87-020-465-080 DIODE,1SS133
SD-R10-451-0AA DIODE,B10A45V1
SD-D01-000-9CB DIODE,EG01AW
SD-R18-020-9AA DIODE,ERA18-02KFRB
SD-D22-060-9AA DIODE,ERA22-06
SD-D01-000-9AC DIODE,EU01W
83-NEG-677-080 DIODE,MTZ5.6B
SD-R49-500-9AA DIODE,RB495D
SD-R10-400-9AB DIODE,RL104
87-017-352-010 DIODE,RU3YXLF-C1 100V
SD-R10-400-0AA DIODE,RZ1040
87-070-173-010 DIODE,S1WBA60
87-070-334-070 ZENER,MTZ10B
SD-Z51-000-9HA ZENER,MTZ5.1B 0.5W
SM-TZ6-8CT-000 ZENER,MTZ6.8C
SD-Z62-000-9BC ZENER,MTZJ6.2B
MAIN C.B
C204 SC-H71-06C-611 C-CAP,10UF-6.3V
C207 SC-H71-06C-611 C-CAP,10UF-6.3V
C213 SC-H71-06C-611 C-CAP,10UF-6.3V
C214 SC-H71-06C-611 C-CAP,10UF-6.3V
C215 SC-H71-06C-611 C-CAP,10UF-6.3V
C216 SC-H71-06C-611 C-CAP,10UF-6.3V
C218 SC-H71-06C-611 C-CAP,10UF-6.3V
C219 SC-H71-06C-611 C-CAP,10UF-6.3V
C220 SC-H81-07C-621 C-CAP,100UF-6.3V
C224 SC-H71-06C-611 C-CAP,10UF-6.3V
C226 SC-H71-06C-611 C-CAP,10UF-6.3V
C230 SC-H71-06C-611 C-CAP,10UF-6.3V
C302 SC-H81-07C-691 C-CAP,100UF-6.3V
C310 SC-H71-06F-621 C-CAP,10UF-16V
C311 SC-H71-06F-621 C-CAP,10UF-16V
C708 SC-H71-06C-611 C-CAP,10UF-6.3V
C709 SC-H82-27D-611 C-CAP,220UF-10V
C712 SC-H71-06C-611 C-CAP,10UF-6.3V
C713 SC-H71-06C-611 C-CAP,10UF-6.3V
C714 SC-H71-06F-621 C-CAP,10UF-16V
C718 SC-H71-06C-611 C-CAP,10UF-6.3V
CE201 SC-H84-76C-611 C-CAP,47UF-6.3V
CE202 SC-H84-76C-611 C-CAP,47UF-6.3V
CE203 SC-H84-76C-611 C-CAP,47UF-6.3V
CE205 SC-H84-76C-611 C-CAP,47UF-6.3V
CE206 SC-H84-76C-611 C-CAP,47UF-6.3V
CE210 SC-H84-76C-611 C-CAP,47UF-6.3V
CE211 SC-H84-76C-611 C-CAP,47UF-6.3V
CE221 SC-H84-76C-611 C-CAP,47UF-6.3V
CE223 SC-H84-76C-611 C-CAP,47UF-6.3V
CE228 SC-H84-76C-611 C-CAP,47UF-6.3V
CE609 SC-H81-07F-611 C-CAP,100UF-16V
CE610 SC-H81-07F-611 C-CAP,100UF-16V
CE710 SC-H84-76C-611 C-CAP,47UF-6.3V
X101 S2-12H-B20-02A CCR20.0MC6T 20MHz
X301 S2-02R-427-01G C-RESO 27MHZ
JUNCTION C.B
CE450 87-010-140-080 CAP,E 47-16V
CE451 87-010-140-080 CAP,E 47-16V
CE452 87-010-140-080 CAP,E 47-16V
CE453 87-010-140-080 CAP,E 47-16V
R451 SR-D01-01H-633 RES,1-1/2W
R452 SR-D01-01H-633 RES,1-1/2W
TIMER C.B
C500 SC-E22-73D-638 CAP,E 220-10V
C502 SC-E10-63F-638 CAP,E 10UF-16V
C506 SC-E47-63J-638 CAP,E 47UF-35V
C507 SC-E10-63F-638 CAP,E 10UF-16V
C512 87-010-140-080 CAP,E 47-16V
C513 87-010-140-080 CAP,E 47-16V
DIG501 S3-02H-V00-1D0 7-BT-259GK DH
RC501 S7-12R-083-8GA TSOP1238UQ1
SW501 S5-562-19B-000 SW,SKHV10910B
SW502 S5-562-19B-000 SW,SKHV10910B
SW503 S5-562-19B-000 SW,SKHV10910B
SW504 S5-562-19B-000 SW,SKHV10910B
SW505 S5-562-19B-000 SW,SKHV10910B
SW506 S5-562-19B-000 SW,SKHV10910B
SW507 S5-562-19B-000 SW,SKHV10910B
SW510 S5-562-19B-000 SW,SKHV10910B
SW511 S5-562-19B-000 SW,SKHV10910B
SW512 S5-562-19B-000 SW,SKHV10910B
SW513 S5-562-19B-000 SW,SKHV10910B
SW514 S5-562-19B-000 SW,SKHV10910B
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REF. NO
PART NO.
KANRI
DESCRIPTION
NO.
REF. NO
PART NO.
KANRI
DESCRIPTION
NO.
TRANSISTOR ILLUSTRATION
X501 S6-160-20P-000 CSA6.00MGU MURATA
JACK C.B
CV1 87-010-060-080 CAP,E 100-16V
CV10 SC-E10-86F-630 CAP,E 1000-16V
JACK1 S6-12H-K26-02A TOTX178
JACK2 S5-720-75A-000 BJP-202L
JACK3 S6-12R-IH0-05G PJ6031MG
JACK4 S6-12R-BH0-08A YKF51-5506 4P
KEY C.B
LED501 SD-L32-531-9AA LED SPR325MVWT31(GRN)
SW508 S5-562-19B-000 SW,SKHV10910B
POWER C.B
C901 S6-240-88B-000 CAP,0.1UF-250V
C901 S6-240-88F-000 CAP,PCX2 275V 0.1UF,M
C903 87-016-099-090 CAP,E 100-200V
C905 87-016-375-010 CAP,0.01UF-630V
C906 S6-240-87B-000 CAP,100P-1KV
C911 87-010-403-040 CAP,E 3.3-50V
C913 S6-240-86B-000 CAP,0.01-400V
C914 S6-240-86B-000 CAP,0.01-400V
C916 87-010-387-010 CAP,E 470UF-25V
C918 87-010-112-080 CAP,E 100-16V
C919 87-010-408-080 CAP,E 47-50V
C921 SC-E22-76F-638 CAP,E 220UF-16V
C923 87-010-237-910 CAP,E 1000UF-16V
C924 87-010-237-910 CAP,E 1000UF-16V
C925 87-010-375-080 CAP,E 330-10V
C926 87-010-408-040 CAP,E 47UF-50V
C927 87-010-408-080 CAP,E 47-50V
C929 87-010-112-080 CAP,E 100-16V
C932 SC-E47-7CD-638 CAP,E 470UF-10V
C934 SC-E47-7CD-638 CAP,E 470UF-10V
!F901 S5-850-03P-000 5TT 250V1.6A BEL
!F901 S5-850-27B-000 FUSE,1600MA 250V
!IC903 S2-309-024-040 SENSOR LTV-817B
!IC903 S6-570-62B-000 SENSOR PC123Y
!L901 S6-161-45E-000 FILTER KSE-145E
!L901 S6-161-45G-000 FL SHT LFSQ2215V4-04220
L902 S6-330-88G-000 COIL,CHOCK TP 5MM
L903 S6-330-88D-000 COIL,20UH
R901 S6-140-07R-000 RES,2.7-2W
R904 SR-S33-02K-619 RES,M/F 33K-2W
R910 SR-S12-00J-619 RES,M/F 120-1W
R911 SR-S01-01K-619 RES,1-2W
R922 SR-S12-00J-619 RES,M/F 120-1W
!T901 S6-420-21G-000 KSE-021G
!V901 S6-560-04F-000 SVR681D10A SAMYANG 680V
!V901 S6-560-04C-000 V SVC681D-10A
•
Regarding connectors, they are not stocked as they are not the initial order items.
The connectors are available after they are supplied from connector manufacturers upon the order is received.
8 8
A
Resistor Code
Chip Resistor Part Coding
Figure
Value of resistor
Chip resistor
Wattage
Type
Tolerance
1/16W
1/10W
1/8W
1608
2125
3216
5%
5%
5%
CJ
CJ
CJ
Form
L
W
t
1.6
0.8
0.45
2
1.25
0.45
3.2
1.6
108
118
128
: A
: A
CHIP RESISTOR PART CODE
0.55
Resistor Code
Dimensions (mm)
Symbol
1/16W
1005
5%
CJ
1.0
0.5
0.35
104
L
t
W
ECB
KRA105M
KRC105M
KRC103M
ECB
KSB1151
BCE
KSE13005F
UMX1N
UMZ1N
C2B1
E1
E2
B2C1
B
E
C
2SA1037K
KTA1504S
KTA1505S
KTC3198
KTC3875S
KTC4419
KTD1304S
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BLOCK DIAGRAM-1 (OVERALL)
M
M
POWER CONTROL
RXDO/TXDO/SCKO
LOADING DRIVE
SENS, FOK, SLD_FG,
MSDAT0,DEFECT,DSP_SENSE,
SQSO, SQCK, AO[0:5]
XLAT, S_CLK, S_DATA, DO[0:7]
27MHz
VDATA[0:7]
Hsync
Vsync
Composite, Y, C
Component
DVD_LDQM, DVD_SD_CS1
DVD_MA[0:11]
DVD_MD[0:15]
DVD_SD_CS0,
DVD_UDQM
DVD_DATA[0:7]
SDCLKI, ZISENB
REQZI
MCK
(33.8688MHz)
DA_DATA,
DA_LRCK,
DA_BCK
DA_XCK
DVD_SD_CAS,
DVD_SD_RAS
DVD_SD_CLK
DVD_MWE
D[00:07]
A[00:02]
S_CLK, S_DATA,
DPLL_L
IIC_DATA,
IIC_CLK
MPEG RST
DAC_L0,
S_CLK
S_DATA
L
L
AUDIO
OUT
VIDEO OUT
R
Composite
C
Y
R
FILTER
AMP
DA_DATA,
DA_LRCK,
DA_BCK
27MHz
X-TAL
SLD_FG
SPINDLE_FG
FDO,TDO,
FMO
MON, SPINDLE_DRV
TEBAL, FEBAL,
DPOCTL, EQF, EQB
FE, TE, RFRP, SBADD, DVD/CD RF
MIRR, TZC
ICADDR[0:8]
ICDATA[00:15]
RFRP,
TE, Vref
DVD : A, B, C, D
DVD : RF
CD : A, B, E, F
spindle
Loading
focus, tracking, sled
SPINDLE
MOTOR
DISC
LOADING
MOTOR
OPEN S/W
CLOSE S/W
LIMIT S/W
DECK MECHANISM
AC 120V
60Hz
-22.5V
-27V
-21.8V
+9V
+5VA
+5VD
+5VU
AGND,GND,UGND
PICK
UP
Pb
Pr
Y
FILTER
IC308
PLL1700
CLOCK
GENERATROR
IC400
BA6859FP
SPINDLE
MOTOR
DRIVER
IC401
BA5983
POWER
DRIVER
IC206
DVDSP-3301
CD/DVD DSP
DVD SERVO
DRAM
256K x 16bit
Comp.
POWER
BOARD
IC801
BT861A
NTSC/PAL
Encoder
IC703
PCM1716
AUDIO
DAC
IC108
HD6417034
IC301
ZiVA-3
MPEG A/V
Decoder
IC306
GM72V1621
1M X 16bit
SDRAM
IC307
GM72V1621
1M x 16bit
SDRAM
IC201
TA1254F
RF SIGNAL
PROCESSOR
IC500
LC866112
FL DISPLAY
KEY INPUT
REMOCON
RECEIVER
DRAM
FLASH
MEMORY
RFZ HOLD
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BLOCK DIAGRAM-2 (POWER)
TRANS
Q901
KTC4419
SWITCHING IC
LINE FILTER
RECTIFIER(FLD)
RECTIFIER(14V)
RECTIFIER(5.2V)
FEED B.
LPF
REG(8V)
F+
F-
-24V
12V
8V
D5V
A5V
U5V
PWR ON/OFF
AC120V
RECTIFIER(10V)
LPF
RECTIFIER
LPF
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BLOCK DIAGRAM-3 (RF/DSP/SERVO)
PICK
UP
M/D
UCOM
I/F
UCOM
I/F
UCOM
I/F
MPEG
I/F
MPEG
I/F
DVD : A,B,C,D
RFRP,
TE, Vref
FE,TE,RFRP,SBADD
RFZ_HOLD
DVD/CD RF
TEBAL, FEBAL,
DPOCTL, EQF, EQB
5
4
MIRR,TZC
SENS, FOK, SLD_FG,
MSDATO, DEFECT, DSP_SENSE
5
2
3
8
8
6
SQSO, SQCK
REQZI
XLAT,S_CLK, S_DATA
DO[0:7]
AO[0:5]
ZO[0:7]
2
SDCLKI, ZISENB
MCK (33.8688MHz)
FDO, TDO, FMO
SLD_FG
SPINDLE_FG
loading drive
focus, tracking, loading, sled
spindle
MON, SPINDLE_DRV
ICDATA[00:15]
ICADDR[0:8]
16
9
3
2
4
4
DVD : RF
CD : A, B, E,F
IC201
TA1254AF
RF Signal
Processor
IC206
GDC25D801
CD/DVD DSP
IC400
BA6859AFP
Spindle
Motor Driver
IC401
BA5983
Power Driver
IC205
DRAM
256K x 16bit
IC204
comp.
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BLOCK DIAGRAM-4 (AUDIO)
µ-com I/F
(IC108)
MPEG I/F
(IC301)
TO
JACK BOARD
CH 1/2 : DOWNMIX Lt / Rt
Lt
Rt
R0
L0
MPEG_RST
S_DATA
S_CLK
DAC_L0
DA_LRCK
DA_BCK
DA_XCK
DA_DATA0
IC703
PCM1716
Audio DAC
IC704
LPF &
Buffer
NJM4580M
OP AMP
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17
BLOCK DIAGRAM-5 (MPEG)
DVD_DATA[0:7]
SDCLK1,ZISENB
REQZ1
A[00:02]
D[00:07]
MPEG_ERROR
IIC_DATA, IIC_CLK
DVD_MD[0:15]
DVD_MA[0:11]
DVD_SD_CAS
DVD_SD_RAS
DVD_SD_CLK
DVD_MWE
DVD_SD_CS0, DVD_UDOM
8
4
2
8
2
2
4
16
12
2
DVD_LDOM,
DVD_SD_CSI
MCK
S_CLK, S_DATA, DPLL_L
DA_DATA[0:3]
DA_BCK
SPDIF
HSYNC, VSYNC
2
8
VDATA[0:7]
DA_XCK
MPEG_CLK
Y/C
COMPOSITE1
Pr
Pb
Y
3
DSP
I/F
µ-COM
I/F
IC301
CL61330
MPEG A/V
Decoder
IC801
BT861A
NTSC/PAL
Encoder
IC306
GM72V1621
1M x 16bit
SDRAM
IC307
GM72V1621
1M x 16bit
SDRAM
IC308
PLL1700
CLOCK
GENERATROR
27MHz
X-TAL
UCOM
I/F
VIDEO
I/F(A/V)
AUDIO
I/F(A/V)
SERVO
I/F
BLOCK DIAGRAM-6 (SYSTEM CONTROL)
MPEG
I/F
A/V
I/F
FRONT
I/F
SERVO
I/F
DSP
I/F
D[00:07], A[00:02], IIC_CLK, IIC_DATA, SCLK0,
MPEG_INT
ECHO, MIC_A, DISC_A, S_DATA, S_CLK
BCA_CODE, SPINDLE_FG, SLD_FG,
D[00:07], A[00:05], E_SIN, E_CLK
LOAD FR, F/R, LOCK, DEFECT, FOK,
DSP_SENSE
8
D[00:07]
EXP_W2,
/PWR_CLT
D[00:15]
D[00:15]
D[00:15]
A[01:19]
A[19:21]
/IOCS1, /WR
SENS_MCOM,
MICOM_WAIT
2
2
D[00:04]
MICOM_RESET
PWR_CTL,
SENS, LIMIT_SW,
MIC_ON, CLOSE_SW,
OPEN_SW, MPEG_WAIT,
ZISERR
MPEG_ERROR,
DAC_L0,
RF_LAT,
/DSP_CS,
/MPEG_CS,
/PP_CS
6
8
5
3
A[01:09]
19
16
9
16
16
A[00:21] 22
2
MPEG_RST,
E_DR,
/ZOOM_RST,
/S_XRST,
XLAT,
ACT_MUTE,
V_MUTE,
A_MUTE
8
IIC_CLK,
IIC_DATA
2
IC114
EEPROM
AT24C02
IC101
XC9536
EXPANDER
IC106
FLASH
MEMORY
512K x 16
IC102
74HC374
IC107
DRAM
256K x 16
IC108
HD6417034
MAIN µ-COM
w w w
.
x i a o y u 1 6 3 .
c o m
Q Q
3 7 6 3 1 5 1 5 0
9
9
2
8
9
4
2
9
8
T E L
1 3 9 4 2 2 9 6 5 1 3
9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
Q
TEL 13942296513 QQ 376315150 892498299
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20
19
WIRING-1 (MAIN: COMPONENT SIDE)
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
I
J
TO/FROM
POWER C.B
CON902
TO/FROM
JUNCTION C.B
CN402
TO/FROM
JUNCTION C.B
CN404
TO/FROM JACK C.B
CON07
TO/FROM JACK C.B
CON06
MAIN C.B
(COMPONENT SIDE)
TO/FROM TIMER C.B
CN507
NOTE
B
E
C
E
Cxxx
Rxxx
Lxxx
1
1
1
10
1
1
2
22
21
1
2
22
21
5
1
5
5
8
1
4
19
2
2
26
25
20
E
E
E
E
R801
R727
R399
R364
R366
R365
R307
R729
R732
R726
R723
R721
C713
C715
C712
CE711
R714
R787
156
157
208
1
52
53
104
105
R309
R312
R385
R384
1
52
53
104
105
156
157
208
C227
1
16
17
32
33
48
49
64
1
5
15
1
2
14
R184
R191
C128
1
112
85
84
57
56
29
28
1
1
15
14
2
20
21
40
w w w
.
x i a o y u 1 6 3 .
c o m
Q Q
3 7 6 3 1 5 1 5 0
9
9
2
8
9
4
2
9
8
T E L
1 3 9 4 2 2 9 6 5 1 3
9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
Q
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21
WIRING-2 (MAIN: CONDUCTOR SIDE)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A
B
C
D
E
F
G
H
I
J
MAIN C.B
(CONDUCTOR SIDE)
1
1
24
25
48
4
5
8
1
4
5
8
1
4
5
8
1
4
5
8
R193
R188
E
E
1
1
40
20
21
11
12
22
23
33
34
44
1
1
1
20
21
40
41
60
61
80
5
10
11
20
E
E
E
C202
R823
E
E
E
E
E
E
R777
CE712
R717
R736
1
14
15
28
1
3
4
6 E
C728
1
1
1
25
26
50
1
25
26
50
10
11
20
1
3
4
6
4
5
8
NOTE
B
E
C
E
Cxxx
Rxxx
Lxxx
w w w
.
x i a o y u 1 6 3 .
c o m
Q Q
3 7 6 3 1 5 1 5 0
9
9
2
8
9
4
2
9
8
T E L
1 3 9 4 2 2 9 6 5 1 3
9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
Q
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23
SCHEMATIC DIAGRAM-1 (MAIN 1/5)
w w w
.
x i a o y u 1 6 3 .
c o m
Q Q
3 7 6 3 1 5 1 5 0
9
9
2
8
9
4
2
9
8
T E L
1 3 9 4 2 2 9 6 5 1 3
9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
Q
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25
SCHEMATIC DIAGRAM-2 (MAIN 2/5)
w w w
.
x i a o y u 1 6 3 .
c o m
Q Q
3 7 6 3 1 5 1 5 0
9
9
2
8
9
4
2
9
8
T E L
1 3 9 4 2 2 9 6 5 1 3
9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
Q
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27
SCHEMATIC DIAGRAM-3 (MAIN 3/5)
w w w
.
x i a o y u 1 6 3 .
c o m
Q Q
3 7 6 3 1 5 1 5 0
9
9
2
8
9
4
2
9
8
T E L
1 3 9 4 2 2 9 6 5 1 3
9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
Q
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29
SCHEMATIC DIAGRAM-4 (MAIN 4/5)
w w w
.
x i a o y u 1 6 3 .
c o m
Q Q
3 7 6 3 1 5 1 5 0
9
9
2
8
9
4
2
9
8
T E L
1 3 9 4 2 2 9 6 5 1 3
9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
Q
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31
SCHEMATIC DIAGRAM-5 (MAIN 5/5)
w w w
.
x i a o y u 1 6 3 .
c o m
Q Q
3 7 6 3 1 5 1 5 0
9
9
2
8
9
4
2
9
8
T E L
1 3 9 4 2 2 9 6 5 1 3
9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
Q
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33
SCHEMATIC DIAGRAM-6 (JACK)
w w w
.
x i a o y u 1 6 3 .
c o m
Q Q
3 7 6 3 1 5 1 5 0
9
9
2
8
9
4
2
9
8
T E L
1 3 9 4 2 2 9 6 5 1 3
9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
Q
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1
2
3
4
5
6
7
8
9
10
11
12
13
14
A
B
C
D
E
F
G
H
I
J
K
36
35
WIRING-3 (JUNCTION/JACK)
M3
(LOADING MOTOR)
TO/FROM
MAIN C.B
CON201
JACK C.B
JUNCTION C.B
TO/FROM
POWER C.B
CON904
PICK UP
ASSY
TO/FROM
MAIN C.B
CON201
TO/FROM
MAIN C.B
CON801
TO/FROM
MAIN C.B
CON202
VIDEO
OUT
OPTICAL
COAXIAL
DIGITAL OUT
JACK04
AUDIO OUT
L
R
2
1
Pb
Pr
L
R
Y
S-VIDEO
OUT
OPEN/CLOSE
SWITCH
NOTE
E
C
B
M
M2
(SLED MOTOR)
M
SPINDLE
MOTOR
M
SW1
M1
INSIDE
LIMIT
SW
1
3
w w w
.
x i a o y u 1 6 3 .
c o m
Q Q
3 7 6 3 1 5 1 5 0
9
9
2
8
9
4
2
9
8
T E L
1 3 9 4 2 2 9 6 5 1 3
9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
Q
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37
SCHEMATIC DIAGRAM-7 (JUNCTION)
w w w
.
x i a o y u 1 6 3 .
c o m
Q Q
3 7 6 3 1 5 1 5 0
9
9
2
8
9
4
2
9
8
T E L
1 3 9 4 2 2 9 6 5 1 3
9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
Q
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1
2
3
4
5
6
7
8
9
10
11
12
13
14
A
B
C
D
E
F
G
H
I
J
K
40
39
WIRING-4 (TIMER/KEY/POWER)
TO/FROM MAIN C.B
CON107
TO/FROM
MAIN C.B
CON999
TO/FROM
JUNCTION C.B
CN401
POWER C.B
KEY C.B
TIMER C.B
SW508
POWER
SW512
SW510
ENTER
SW511
SW513
SW513
SW503
SW504
SW507
OPEN/CLOSE
SW502
MENU
SW505
STOP
SW506
PLAY
SW501
PAUSE
SW514
AC 120V
60Hz
1
5
1
4
B C E
B
C
E
1
1
1
2
2
3
4
4
6
2
3
4
7
10
15
BD901
T901
L901
F901
1
1
42
3
REMOTE
SENSOR
NOTE
E
C
B
w w w
.
x i a o y u 1 6 3 .
c o m
Q Q
3 7 6 3 1 5 1 5 0
9
9
2
8
9
4
2
9
8
T E L
1 3 9 4 2 2 9 6 5 1 3
9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
Q
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42
41
SCHEMATIC DIAGRAM-8 (TIMER/KEY)
w w w
.
x i a o y u 1 6 3 .
c o m
Q Q
3 7 6 3 1 5 1 5 0
9
9
2
8
9
4
2
9
8
T E L
1 3 9 4 2 2 9 6 5 1 3
9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
Q
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43
SCHEMATIC DIAGRAM-9 (POWER)
w w w
.
x i a o y u 1 6 3 .
c o m
Q Q
3 7 6 3 1 5 1 5 0
9
9
2
8
9
4
2
9
8
T E L
1 3 9 4 2 2 9 6 5 1 3
9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
Q
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45
WAVE FORM
1
IC201 Pin ( (LVL) SBADD
VOLT/DIV: 500mV
TIME/DIV:
2mS
IC201 Pin ¡ (FEO) Focus Error
VOLT/DIV: 2.9V
TIME/DIV:
2mS
2
IC201 Pin ) (TEO)
VOLT/DIV: 2.2V
Tracking Error
TIME/DIV:
2mS
3
IC201 Pin ) (TEO)
VOLT/DIV: 2.27V
VBR Tracking Error
TIME/DIV:
500µS
4
IC201 Pin • (RFO)
VOLT/DIV: 0.5V
TIME/DIV:
0.1µS
5
IC206 Pin (A OUT3)
VOLT/DIV: 2.12V
SLED Drive (FMO)
TIME/DIV:
10mS
6
IC201 Pin ¡ (FEO)
VOLT/DIV: 200mV
Focus Error (In Focus search)
TIME/DIV:
100mS
IC206 Pin (A OUT1)
VOLT/DIV: 2.14V
Focus Drive (FDO)
TIME/DIV:
100mS
7
IC801 Pin #-^ (P0-P3)
VOLT/DIV: 280mV
IC801 Pin (-™ (P4-P7)
TIME/DIV:
500µS
MPEG Data
88
83
Tek Stop : 1 00kS/s
3290 Acqs
M 500µs
CH1
280/mV
Record
Length
Fit to Screen
OFF
Time Base
Main
Trigger
Position
50%
Horiz
Scale
(/div)
Horiz
Pos
FastFrame
Setup
more
1 of 3
3
Ch3
1.00V
[ T ]
[ T ]
Record
Length
2500
T
2500
points in
50divs
1000
points in
20divs
500
points in
10divs
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@
IC801 Pin (CLK IN)
VOLT/DIV: 280mV
MPEG Clock
TIME/DIV:
500µS
#
IC801 Pin ≤ (VSYNC)
VOLT/DIV: 280mV
Vertical SYNC
TIME/DIV:
5mS
$
IC801 Pin ∞ (HSYNC)
VOLT/DIV: 280mV
TIME/DIV:
20µS
%
IC801 Pin + (DACF)
VOLT/DIV: 500mV
Component Pb
TIME/DIV:
20µS
8
IC801 Pin (DACC)
VOLT/DIV: 500mV
Composite
TIME/DIV:
20µS
9
IC801 Pin (DACB)
VOLT/DIV: 500mV
Chrominance
TIME/DIV:
20µS
0
IC801 Pin (DACA)
VOLT/DIV: 500mV
Luminance
TIME/DIV:
20µS
!
IC801 Pin (SID)
VOLT/DIV: 2.06V
IC801 Pin (SIC)
TIME/DIV:
25mS
SDA/SCL
58
Tek Stop : 2.50MS/s
4 Acqs
M20.0µs
2 Apr 1999
14:47:27
Glitch
Ch1
Ch3
500mV
[T ]
T
3
59
75
76
Tek Stop : 1 00kS/s
3290 Acqs
M 500µs
CH1
280/mV
Edge Slope
Type
<Edge>
Source
Ch1
Coupling
DC
Level
280mV
Mode
&
Holdoff
3
Ch3
1.00V
[ T ]
[ T ]
Slope
T
Tek Stop : 10.0kS/s
13 Acqs
M 5 .00ms CH1
280/mV
Edge Slope
Type
<Edge>
Source
Ch1
Coupling
DC
Level
280mV
Mode
&
Holdoff
3
Ch3
1.00V
[ T ]
Slope
T
Tek Stop : 2.50MS/s
7 Acqs
M 20.0µs
CH1
280/mV
Edge Slope
Type
<Edge>
Source
Ch1
Coupling
DC
Level
280mV
Mode
&
Holdoff
3
Ch3
1.00V
[ T ]
Slope
T
71
57
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^
IC801 Pin , (DACE)
VOLT/DIV: 500mV
Component Pr
TIME/DIV:
20µS
&
IC801 Pin < (DACA)
VOLT/DIV: 500mV
Component Y
TIME/DIV:
20µS
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48
TROUBLE-SHOOTING
1. Power Circuit
•
Input Voltage: 120V
•
It is possible to malfunction, if the unload condition is left for a long time when power is on.
(More than Dummy load 100mA)
•
A Primary side is abnormal when the fuse is short, secondary side is abnormal when the IC103 oscillates intermittently.
•
The resistor value of both terminal is measured with DVM crossing each other to check the each element is normal or abnormal.
(It is normal when the numerical value is different each other.)
START
Is F901 normal?
Is IC901 Pin 3
switching normally?
<Fig-3-1>
Is CN903 Pin 3 5.2V?
Does oscillate
continuously when
the CON903 is
disconnected ?
IC901 Pin 3
Normal switching waveform on the
stand-by mode at the AC110V
Check the GND of C901 and
IC901 Pin 3 with oscilloscope.
When IC901
oscillating
Secondary side
is abnormal.
Are D908, D909,
D907, D910, D906
and D905 normal?
Front Circuit
Board is
abnormal
Is CON903 Pin 3
5.2V?
(A)
Replace
defective
parts.
Replace Q908
and Q909.
Replace
IC902.
Check Q904
and ZD903.
After connect
CON903
Pin 1, 3 short.
Are CON902
Pin 5, 6 and
9 5V?
Is CON904
Pin 3 8V?
Is CON902
Pin 3 12V?
Are CON903
Pin 5 -24V, Pin 7 -20V and
Pin 8 -16V?
To (A).
A primary side is abnormal.
In condition of DC140V.
(Feedback is abnormal)
Is IC905
normal?
Check or
replace
D908.
Are R922, C927, R921
and R918 normal?
Is voltage of
BD901 140V?
Are R907, D902,
D903 and R902
normal?
Are D901, R904,
R905 and R906
normal?
Is PC901 normal?
Replace defective
parts.
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
END
END
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2. µ-COM Circuit
A. No Power
POWER ON
Power RED LED on?
NO
NO
NO
NO
NO
NO
NO
OK
NO
NO
NO
YES
YES
YES
1
1
YES
YES
YES
YES
OK
YES
YES
A
A
Refer to Front Part.
Does Bar appear
at FLD?
Do all five Bars
appear?
Does Logo appear
on the screen?
Is oscillation of
X101 normal?
Check the oscillation
Are IC107 Pin $, •�
and ª normal?
Check short.
Replace IC107
or IC108.
Is CON107
connected normally?
Check power.
(Refer to power)
If power is
normal
Is CON107 Pin 6
normal?
Reconnect it.
The
waveform on A [00:21]
and D [00:15] of IC108
normal?
Check short
Are IC101
Pin 7, 8 normal?
Replace IC101.
Replace Main B/D.
Refer to Front Part
END
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AUDIO ABNORMAL
Check Audio jack.
Check PLL FC of
MPEG part.
Refer to Audio part.
Refer to MPEG part.
Replace B/D.
YES (If OK)
YES (If OK)
YES (If OK)
YES (If OK)
END
B. Audio abnormal
C. Video abnormal
VIDEO ABNORMAL
Check Video jack.
Refer to Video part.
Refer to Encoder part.
Refer to MPEG part.
Replace B/D.
YES (If OK)
YES (If OK)
YES (If OK)
YES (If OK)
END
YES (If OK)
YES
YES
YES
OPEN/CLOSE ABNORMAL
Check Front.
NO
NO
Check the
connection of
CON107.
Reconnect it.
Check IC101
Pin #, $.
Check the connection of MD.
Refer to SERVO part.
D. Open/Close abnormal
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E. Picture abnormal
F. Disc Error
PICTURE ABNORMAL
Check the disc.
Refer to Servo part
Check PLL IC of MPEG part
Check DSP
Check MPEG
If OK
YES (If OK)
YES (If OK)
YES (If OK)
Replace B/D
END
DISC ERROR
Check Disc
Refer to Servo part
Replace B/D
YES (If OK)
YES (If OK)
END
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52
3. MPEG Circuit
Power is on
Does LG Logo appear
on the screen?
Does the
moving picture of the DVD Disc
play on the screen
normally?
Does the
moving picture of the video
CD play on the screen
normally?
Does the
audio sound output
normally?
END
Check power & clock.
Is MPEG data
signal normal?
Is error signal normal?
Is MPEG data
signal normal?
I OPTION
If included VCD function.
Is Clock normal?
Does the audio
sound output from MPEG
decoder?
Check CD/DVD DSP
output signal.
Check MPEG Decoder
input signal.
Check CD/DVD DSP
output signal.
Check MPEG Decoder
input signal.
Check CD/DVD DSP
output signal.
Check MPEG Decoder
input signal.
Check clock signal
Check clock signal
B
A
C
D
E
F
G
H
I
YES
YES
YES
YES
YES
YES
YES
YES
YES
NO
NO
NO
OK
OK
OK
OK
NO
NO
NO
NO
NO
YES
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2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
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4. Front Circuit (Digitron & key)
START
NO
NO
NO
NO
NO
NO
NO
CD
NO
NO
NO
NO
NO
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
Power on.
LED ON?
Is Digitron on
normally?
Do all
the buttons work
normally?
Does remote control
work normally?
Complete repairing
Front B/D.
Check waveform of
IC500 Pin #.
Check and replace R516,
R507, R506, R500, R505,
R504, R512 and R503.
Does pulse
waveform of RE500
Pin 3 appear?
Is IC500
Pin ≤ connected to
RE500 Pin 3?
Replace IC500.
Is oscillation of
X501 normal?
Check waveform
of IC500 Pin 6.
Is waveform of IC500
Pin normal?
Solder defective parts again
Check Power.
Replace IC501.
Check waveform
of IC500 Pin #.
Check waveform
of Q500 Pin 2.
Replace IC500.
Replace LED501.
Solder Key part.
Replace Q500.
Is RE500 Pin 2
5V?
Solder defective parts
Replace RE500
Re-solder.
76
Recheck
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2
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2
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9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
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5. RF/Servo Circuit
A.
CHECK POINT (General)
Does signal goes
“High” to IC206 Pin when
the power is on?
YES
NO
NO
NO
NO
NO
YES
YES
YES
YES
END
Does signal
pulse input to IC206 Pin ,
when the power
is on?
Does TTL
pulse output to IC206
Pin , ?
Is IC206
Pin , , , voltage
about 2.2V?
Check “2.µ-COM Part”.
Does
33.8688MHz clock input
to IC206 Pin ?
Replace IC206
(IC206 soldering or IC defect).
Replace IC700
(IC700 soldering or IC defect).
Replace X301 or IC308
(30MHz clock defect)
58
59
194
140
142
63
83
84
88
89
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2
8
9
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2
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9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
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B.
END
NO
NO
NO
YES
YES
YES
NO
NO
NO
YES
YES
YES
No disc
Power on
Does tray open
or close?
Fig-1. SLED Driver waveform
Does the pick-up
slide inner or outer
track?
Fig-2. Focus Driver waveform
Does
the pick-up lens move up
and down?
Slide the pick-up to
inner track.
Check loading Part.
Push Pick-up to inner track
to the end by hand.
Does
CON202 Pin & change
high to low?
Pressing
the open/close key repeatedly,
check the voltage of CON202 Pin 9
change 0V to 5V
Junction Board
Does
the voltage change at
IC401 Pin %, ^ more than 2V on the
basis of 4.5V?
DECK assembly is defective.
DECK assembly is defective.
(Limit sw)
check µ-COM Part.
Replace IC401.
Check SLED Driver output.
IC206 Pin IC401 Pins *, &.
IC206 Pin no output : IC206 is defective
IC401 Pin * no output : IC401 is defective
Check Focus Driver output.
(IC206 Pin , IC401 Pins !, @)
IC206 Pin no output : IC700 is defective
IC401 Pin 1, 2 no output : IC701 is defective
83
88
88
83
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9
2
8
9
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2
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9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
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C.
END
YES
YES
YES
YES
YES
NO
NO
NO
YES
YES
NO
NO
NO
NO
NO
YES
DISC IN
OPEN/CLOSE
FOCUS ON?
Does the disc turn?
IC206 Pin is “High”?
Is OK the track jump.
Does the screen appear?
Check
the focus error moving the
lens up and down. (IC201
Pin ¡)
Does the
TTL level change at IC206
Pin and moving
the lens?
Replace µ-COM or IC206.
Check CON404 Pin 4, 6
Motor turn when the Pin 4 is
less than 1.6V
Video Par is defective.
Check “5.MPEG Circuit.”
Check “7.OSD/Video Circuit.”
Check A
Fig-3. FOCUS ERROR waveform
Check IC201 Pin , , , in DVD Mode
Check IC201 Pin , , , in CD Mode
IC201 no output: Pick-up is defective.
Replace IC206.
Check IC206 and IC403 when the Pin 4 is abnormal
Does the signal
pulse input at IC700 Pin ≥,
• and ª?
µ-COM part is
defective. Check
“2.µ-COM Circuit.”
Replace IC700.
52
53
54
55
58
59
60
61
78
169
132
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2
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9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
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D.
NO
NO
NO
NO
YES
YES
YES
YES
CHECK A
Fig-5. RF
waveform
Check RF Eye-Pattern.
RF: 1.0-2.1V (IC201 Pin •)
No signal: Pick-up is defective
Is the eye-pattern vivid?
Does the
sawtooth waveform emit
at IC201 Pin )?
Does the 1.6V emit?
Replace IC201.
Replace IC206.
Check IC206 Pin .
No signal at IC206: IC206 is defective
• Check IC206 Pin
• Check the clock at the IC206
Pin •, º.
END
• Both are normal: IC206 is defective
Check IC201 Pin , , , in DVD Mode.
Check IC201 Pin , , , in CD Mode.
52
53
54
55
58
59
60
61
84
162
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9
2
8
9
4
2
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9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
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LCD DISPLAY
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2
8
9
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2
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9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
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VID2-7
VDD
GND
VIDCLK
VIDVALID
VIDVACT
VIDHACT
P0-P3
GND
VDDMAX
P4-P7
BLANK
VSYNC
HSYNC
FIELD
GND
VDD
Secondary video input port. Pixel data (TTL compatible) in 8-bit YCrCb format. A
higher index corresponds to a greater bit significance. Data on the VID port is latched
by rising edge of VIDCLK. (Connected to GND.)
Digital power.
Digital ground.
2x pixel clock for secondary video input port. Synchronization circuitry exists for this
port to lock it to the primary video port. (Connected to GND.)
Video data valid qualifier. A logical 1 indicates data on VID [7:0] is valid data. The
sense of this signal is controlled by the VIDVALIDI bit of register 0x1C. (Connected
to GND.)
Vertical active display region. The sense of this signal is controlled by the VIDVACTI
bit of register 0x1C. (Connected to GND.)
Horizontal active pixel signal. A logical 1 indicates data on VID [7:0] is in the
horizontal display region. The sense of this signal is controlled by the VIDHACTI bit
of register 0x1C. (Connected to GND.)
Primary video input port. TTL compatible pixel data in 8-bit YCrCb format. A higher
index corresponds to a greater bit significance. (1) Data is latched on the rising edge of
the system clock.
Digital ground. Refer to the PC Board Considerations section of this
This pin must be tied to the maximum digital input value. Use 3.3 V if only “3.3 V
inputs are used, and 5 V if 5 V inputs are used.”
Primary video input port. TTL compatible pixel data in 8-bit YCrCb format. A higher
index corresponds to a greater bit significance. (1) Data is latched on the rising edge of
the system clock.
Composite blanking control input (TTL compatible). BLANK is registered on the
rising edge of the system clock. The P [7:0] inputs are ignored while BLANK is a
logical 0. The sense of this signal is controlled by the BLANKI bit of register 0x19.
Vertical sync input/output (TTL compatible). As an output (master mode “operation),
VSYNC is output following the rising edge of the system” “clock. As an input (slave
mode operation), VSYNC is registered on the” rising edge of the system clock. The
sense of this signal is controlled by the VSYNCI bit of register 0x19.
Horizontal sync input/output (TTL compatible). As an output (master mode
“operation), HSYNC is output following the rising edge of the system” “clock. As an
input (slave mode operation), HSYNC is registered on the” rising edge of the system
clock. The sense of this signal is controlled by the HSYNCI bit of register 0x19.
Field control output (TTL compatible). FIELD transitions after the rising “edge of the
system clock, two clock cycles following falling HSYNC. The” sense of this signal is
controlled by the FIELDI bit of register 0x19. The state of this pin at power-up
determines the default state of the PCLK_SEL “register. If not loaded, this pin will be
pulled low with an internal pull-down” resistor.
Digital ground.
Digital power.
I
—
—
I
I
I
I
I
—
—
I
I
I/O
I/O
O
—
—
1-6
7
8
9
10
11
12
13-16
17
18
19-22
23
24
25
26
27
28
IC, BT861
Pin No.
Pin Name
I/O
Description
IC DESCRIPTION
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9
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8
0
5
1
5
1
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Pin No.
Pin Name
I/O
Description
29, 30
31-36
37
38
39, 40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
“Alpha blend pins. Provides for 1-, 2-, or 4-bit external blend selection” between video
and graphic overlay data. Signals are latched using the system clock. (Connected to
GND.)
Dedicated graphic overlay port. Pixel data (TTL compatible) in 8-bit YCrCb format.
Signals are latched using the system clock. (Connected to GND.)
Digital ground.
Digital power.
Dedicated graphic overlay port. Pixel data (TTL compatible) in 8-bit YCrCb format.
Signals are latched using the system clock. (Connected to GND.)
Analog ground.
Component chrominance U channel, component blue, or composite video.
Component chrominance V channel, component green, or composite video.
“Component luminance, component red, or optional luma-delayed” composite video.
AGND; the capacitor must be as close to the device as possible to keep lead lengths to
an absolute minimum.
Analog power.
This pin to VAA. The capacitor must be as close to the device as possible to keep lead
lengths to an absolute minimum. COMP1 is used with DACs A/B/C and COMP2 is
used with DACs D/E/F.
Full-scale adjust control pin. Resistors RSET1 and RSET2 connected between these
pins and AGND controls the full-scale output current on the “analog outputs. For
standard operation, use the nominal values shown” under Recommended Operating
Conditions. FSADJ2 controls DACs D/E/F.
Voltage reference pin.
Not used.
Analog ground.
Analog power.
Full-scale adjust control pin. Resistors RSET1 and RSET2 connected between these
pins and AGND controls the full-scale output current on the “analog outputs. For
standard operation, use the nominal values shown” under Recommended Operating
Conditions. FSADJ1 controls DACs A/B/C.
Compensation pin.
Analog power.
DAC bias voltage.
Composite video.
Modulated chrominance video signal or optional luma-delayed composite video.
Luminance video or optional composite video.
Analog ground.
Digital ground.
Alternate slave address input (TTL compatible). A logical 1 corresponds to “write
address of 0x88 and a read address of 0x89, while a logical 0” corresponds to a write
address of 0x8A and a read address of 0x8B. See the Serial Programming Interface
section for more detail. (Connected to GND.)
ALPHA0, 1
OSD0-5
GND
VDD
OSD6 ,7
AGND
DACF
DACE
DACD
VBIAS2
VAA
COMP2
FSADJ2
VREF
N/C
AGND
VAA
FSADJ1
COMP1
VAA
VBIAS1
DACC
DACB
DACA
AGND
GND
ALTADDR
I
I
—
—
I
—
O
O
O
I
O
—
—
—
I
O
—
—
O
O
O
—
—
I
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9
2
8
9
4
2
9
8
0
5
1
5
1
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Pin No.
Pin Name
I/O
Description
RESET
VDD
GND
PGND
XTI
XTO
VPLL
CLKO
CLKIN
VIDFIELD
TTXREQ
TTXDAT
SID
SIC
GND
VDD
VID0, 1
Reset control input (TTL compatible). Setting to zero resets both video “timing
(horizontal, vertical, subcarrier counters to the start of VSYNC of” “first field) and the
serial control interface, and resets the registers. RESET” must be a logical 1 for normal
operation.
Digital power. Refer to the PC Board Considerations section of this
Digital ground.
Dedicated ground for PLL.
Crystal input for genlock PLL. (Not used.)
Crystal output for genlock PLL. (Not used.)
Dedicated power supply for PLL. (Connected to VDD.)
2x pixel clock for the primary video port. Generated by PLL or pass-through from
CLKIN pin. (Not used.)
2x pixel clock input (TTL compatible).
Field indicator for video input port. A logical 1 indicates data is from an odd field. The
sense of this signal is controlled by the VIDFIELDI bit of register 0x1C. (Connected to
GND.)
Teletext request output (TTL compatible). (Connected to VDD.)
Teletext bit stream input (TTL compatible). (Connected to GND.)
Serial interface data input/output (TTL compatible). Data is written to and read from
the device via this serial bus.
Serial interface clock input (TTL compatible). The maximum clock rate is 400 kHz.
Digital ground.
Digital power.
Secondary video input port. Pixel data (TTL compatible) in 8-bit YCrCb format. A
higher index corresponds to a greater bit significance. Data on the VID port is latched
by rising edge of VIDCLK. (Connected to GND.)
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79, 80
I
—
—
—
I
O
—
O
I
I
O
I
I/O
I
—
—
I
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9
2
8
9
4
2
9
8
0
5
1
5
1
3
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7
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1
2-4
5
6
7
8-11
12
13
14
15
16
17
18
19
20
21-26
27
28
29
30
31-35
36
37
38
39
40
41
42
43-46
IC, CL61330
Pin No.
Pin Name
I/O
Description
P100
HDATA0-2
VDD_3.3
HDATA3
VSS
HDATA4-7
VDD_2.5
RESET
VSS
/WAIT
/INT
VDD
/AMWE
VSS
HDATA8-13
VDD
HDATA14
VSS
HDATA15
HADDR12-16
VDD
HADDR17
VSS
HADDR18
VDD
HADDR19
VSS
HADDR20-23
Programmable I/O pins.
8-bit bi-directional host data bus. Host writes data to the decoder Code FIFO via
HDATA [7:0]. MSB of the 32-bit word is written first. The host also reads and writes
the decoder internal registers and local SDRAM/ROM via HDATA [7:0].
3.3-V supply voltage for I/O signals.
8-bit bi-directional host data bus. Host writes data to the decoder Code FIFO via
HDATA [7:0]. MSB of the 32-bit word is written first. The host also reads and writes
the decoder internal registers and local SDRAM/ROM via HDATA [7:0].
Ground for core logic and I/O signals.
8-bit bi-directional host data bus. Host writes data to the decoder Code FIFO via
HDATA [7:0]. MSB of the 32-bit word is written first. The host also reads and writes
the decoder internal egisters and local SDRAM/ROM via HDATA [7:0].
2.5-V supply voltage for core logic.
Hardware reset. An external device asserts RESET (activeLOW) to execute a decoder
hardware reset. “ To ensure proper initialization after power is stable, assert RESET
for at least 20 ms.”
Ground for core logic and I/O signals.
Transfer not complete/data acknowledge. Active LOW to indicate host initiated
transfer is not complete. WAIT is asserted after the falling edge of CS and
reassertedwhendecoderis ready to “complete transfer cycle. Open drain signal,” must
be pulled-up via 1kW to 3.3 volts. Driven high for 10 ns before tristate.
“Host interrupt. Open drain signal, must be pulled-up via 4.7kW to 3.3 volts. Driven
high for” 10 ns before tristate.
3.3-V supply voltage for I/O signals.
Not used.
Ground for core logic and I/O signals.
Programmable I/O pins. Input mode after reset.
3.3-V supply voltage for I/O signals.
Programmable I/O pins. Input mode after reset.
Ground for core logic and I/O signals.
Programmable I/O pins. Input mode after reset.
Programmable I/O pins. Output mode after reset.
3.3-V supply voltage for I/O signals.
Programmable I/O pins. Output mode after reset.
Ground for core logic and I/O signals.
Programmable I/O pins. Output mode after reset.
2.5-V supply voltage for core logic.
Programmable I/O pins. Output mode after reset.
Ground for core logic and I/O signals.
Programmable I/O pins. Output mode after reset.
I/O
I/O
—
I/O
—
I/O
—
I
—
O
O
—
—
—
I/O
—
I/O
—
I/O
I/O
—
I/O
—
I/O
—
I/O
—
I/O
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2
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2
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8
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5
1
5
1
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VDD
BEO
VSS
NC
P101
MDATA15, 0
VDD
MDATA14
VSS
MDATA1, 13, 2
VDD_3.3
MDATA12
VSS
MDATA3
VDD
MDATA11
VSS
MDATA4
VDD
MDATA10
VSS
MDATA5, 9, 6
VDD
MDATA8
VSS
MDATA7
LDQM
UDQM
VDD
/MWE
VSS
SD-CLK
/SD-CAS
/SD-RAS
VDD
SD-CS1
VSS
SD-CS0
VDD
NC
3.3-V supply voltage for I/O signals.
Programmable I/O pins. Output mode after reset.
Ground for core logic and I/O signals.
No Connection
Programmable I/O pins.
Memory data.
3.3-V supply voltage for I/O signals.
Memory data.
Ground for core logic and I/O signals.
Memory data.
3.3-V supply voltage for I/O signals.
Memory data.
Ground for core logic and I/O signals.
Memory data.
2.5-V supply voltage for core logic.
Memory data.
Ground for core logic and I/O signals.
Memory data.
3.3-V supply voltage for I/O signals.
Memory data.
Ground for core logic and I/O signals.
Memory data.
3.3-V supply voltage for I/O signals.
Memory data.
Ground for core logic and I/O signals.
Memory data.
SDRAM LDQM.
SDRAM UDQM.
3.3-V supply voltage for I/O signals.
SDRAM write enable. Decoder asserts active LOW to request a write operation to the
SDRAM array.
Ground for core logic and I/O signals.
SDRAM system clock.
Active LOW SDRAM column address.
Active LOW SDRAM row address.
3.3-V supply voltage for I/O signals.
Active LOW SDRAM bank select.
Ground for core logic and I/O signals.
Active LOW SDRAM bank select.
2.5-V supply voltage for core logic.
No Connection.
Pin No.
Pin Name
I/O
Description
47
48
49
50, 51
52
53, 54
55
56
57
58-60
61
62
63
64
65
66
67
68
69
70
71
72-74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
—
I/O
—
O
I/O
I/O
—
I/O
—
I/O
—
I/O
—
I/O
—
I/O
—
I/O
—
I/O
—
I/O
—
I/O
—
I/O
O
O
—
O
—
O
O
O
—
O
—
O
—
O
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VSS
NC
VDD
MADDR9
VSS
MADDR1, 8, 10
VDD
MADDR7
VSS
MADDR0, 8, 1
VDD
MADDR5
VSS
MADDR2, 4, 3
VDD
MADDR12
VSS
MADDR13
VDD
MADDR14
VSS
MADDR15-17
VDD
MADDR18
VSS
MADDR19, 20
/ROM_CS
P102
NC
VDD
P103
VDD
VSS
VDD
P104
VDD
P105
VDATA0, 1
VDD
Pin No.
Pin Name
I/O
Description
93
94
95
96
97
98-100
101
102
103
104-106
107
108
109
110-112
113
114
115
116
117
118
119
120-122
123
124
125
126, 127
128
129
130
131, 132
133
134, 135
136
137
138
139, 140
141
142, 143
144
Ground for core logic and I/O signals.
No Connection
3.3-V supply voltage for I/O signals.
Memory address.
Ground for core logic and I/O signals.
Memory address.
3.3-V supply voltage for I/O signals.
Memory address.
Ground for core logic and I/O signals.
Memory address.
3.3-V supply voltage for I/O signals.
Memory address.
Ground for core logic and I/O signals.
Memory address.
3.3-V supply voltage for I/O signals.
Memory address.
Ground for core logic and I/O signals.
Memory address.
2.5-V supply voltage for core logic.
Memory address.
Ground for core logic and I/O signals.
Memory address.
3.3-V supply voltage for I/O signals.
Memory address. (Not used.)
Ground for core logic and I/O signals.
Memory address. (Not used.)
Open drain signal, must be pulled-up via 4.7kW to 3.3 volts.
Programmable I/O pins.
No Connection.
3.3-V supply voltage for I/O signals.
Programmable I/O pins.
3.3-V supply voltage for I/O signals.
Ground for core logic and I/O signals.
3.3-V supply voltage for I/O signals.
Programmable I/O pins.
3.3-V supply voltage for I/O signals.
Programmable I/O pins.
Video data bus. Byte serial CbYCrY data synch- ronous with VCLK. At power-up, the
decoder does not drive VDATA. During boot-up, the decoderuses configuration
parameters to drive or 3-state VDATA.
2.5-V supply voltage for core logic.
—
O
—
O
—
O
—
O
—
O
—
O
—
O
—
O
—
O
—
O
—
O
—
O
—
O
O
I/O
O
—
I/O
—
—
—
I/O
—
I/O
O
—
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5
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5
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VDATA2
VSS
P105
VDATA3
VDD
VDATA4
VSS
VDATA5
P107
VDATA6, 7
P108
/HSYNC
/VSYNC
DA-IEC
VDD
DA-DATA0
VSS
DA-DATA1-3
DA-LRCK
DA-BCK
VDD
DA-XCK
VSS
DAI-DATA
DAI-LRCK
Video data bus. Byte serial CbYCrY data synch- ronous with VCLK. At power-up, the
decoder does not drive VDATA. During boot-up, the decoderuses configuration
parameters to drive or 3-state VDATA.
Ground for core logic and I/O signals.
Programmable I/O pins.
Video data bus. Byte serial CbYCrY data synch- ronous with VCLK. At power-up, the
decoder does not drive VDATA. During boot-up, the decoderuses configuration
parameters to drive or 3-state VDATA.
3.3-V supply voltage for I/O signals.
Video data bus. Byte serial CbYCrY data synch- ronous with VCLK. At power-up, the
decoder does not drive VDATA. During boot-up, the decoderuses configuration
parameters to drive or 3-state VDATA.
Ground for core logic and I/O signals.
Video data bus. Byte serial CbYCrY data synch- ronous with VCLK. At power-up, the
decoder does not drive VDATA. During boot-up, the decoderuses configuration
parameters to drive or 3-state VDATA.
Programmable I/O pins.
Video data bus. Byte serial CbYCrY data synch- ronous with VCLK. At power-up, the
decoder does not drive VDATA. During boot-up, the decoderuses configuration
parameters to drive or 3-state VDATA.
Programmable I/O pins.
Horizontal sync. The decoder begins out putting pixel data for a new horizontal line
after the falling (active) edge of HSYNC.
Vertical sync. Bi-directional, the decoder outputs the top border of a new field on the
first HSYNC after the falling edge of VSYNC. VSYNC can accept vertical
synchronization or top/bottom field notification from an external source. (VSYNC
HIGH = bottom fie
Bitstream data in IEC-1937 or PCM data out in IEC-958 format.
3.3-V supply voltage for I/O signals.
PCM data out, eight channels. Serial audio samples relative to DA-BCK clock.
Ground for core logic and I/O signals.
PCM data out, eight channels. Serial audio samples relative to DA-BCK clock.
PCM left-right clock. Identifies the channel for each audio sample. the polarity is
programmable.
PCM bit clock. Divided by 8 from DA-XCK, DA-BCK can be either 48 or 32 times
the sampling clock.
2.5-V supply voltage for core logic.
Audio master frequency clock. Used to generate DA-BCK and DA-LRCK. DA-XCK
can be either 384 or 256 times the sampling frequency.
Ground for core logic and I/O signals.
PCM input data, two channels. Serial audio samples relative to DAI-BCK clock.
PCM input left-right clock.
O
—
I/O
O
—
O
—
O
I/O
O
I/O
I/O
I/O
O
—
O
—
O
O
O
—
I/O
—
I
I
Pin No.
Pin Name
I/O
Description
145
146
147
148
149
150
151
152
153
154, 155
156
157
158
159
160
161
162
163-165
166
167
168
169
170
171
172
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5
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Pin No.
Pin Name
I/O
Description
DAI-BCK
P109
CLKSEL
A_VDD
VCLK
SYSCLK
A-VSS
DVD-DATA0/CD-
DATA
VDD
DVD-DATA1/CD-
LRCK
VSS
DVD-DATA2/CD-
BCK
DVD-DATA3/CD-
C2PO
DVD-DATA4/
CDG_SDATA
PI101
VREQUEST
VSTROBE
VDD
AREQUEST
VSS
V-DACK/ASTROBE
VDD
I
I/O
I
—
I
I
—
I
—
I
—
I
I
I
I/O
O
I
—
O
—
I
—
PCM input bit clock.
Programmable I/O pins.
Clock Select: Internal = VDD, External = VSS
3.3-V analog supply voltage.
Video clock. Clocks out data on input. VDATA [7:0]. Clock is typically 27 MHz.
System clock. Decoderrequires an external 27MHz TTL oscillator. Drive with the
same 27-MHz as VCK.
Analog ground for PLL.
Serial CD data. This pin is shared with DVD compressed data DVD-DATA0. ERROR
200 I Error in input data. If ERROR signal is not available from the DSP it must be
grounded.
3.3-V supply voltage for I/O signals.
Programmable polarity 16-bit word synchronization to the decoder (right channel
HIGH). This pin is shared with DVD compressed data DVD-DATA1.
Ground for core logic and I/O signals.
CD bit clock. Decoder acceptmultipleBCKrates. This pin is shared with DVD
compressed data DVD-DATA2.
Asserted HIGH indicates a corrupted byte. Decoder keeps the previous valid picture
on-screen until the next valid picture is decoded. This pin is shared with DVD
compressed data DVD-DATA3.
DVD parallel compressed data from DVD DSP. When DVD DSP sends 32-bit words,
it must write the
DVD-DATA5/CDG_VFSY
MSB first. CDG-SDATA: CD+G (Subcode) Data.
DVD-DATA6/CDG_SOSI
Indicates serial subcode data input.
DVD-DATA7/CDG_SCLK
CDG-VSFY: CD+G (Subcode) Frame Sync. Indicates
frame-start or composite synchronization input. CDG-S0S1: CD+G (Subcode) Block
Sync. Indicates block-start synchronization input. CDG-SCLK: CD+G (Subcode)
Clock. Indicates subcode data clock input or out-put.
Programmable I/O pins.
Video request. Decoder asserts VREQUEST to indicate that the video input buffer has
available space. Polarity is programmable.
Video strobe. Programmable dual mode pulse. Asynchronous and synchronous. In
Asynchronous mode, anexternal sourcepulses VSTROBE to indicate data is ready for
transfer. In synchronous mode VSTROBE clocks data.
3.3-V supply voltage for I/O signals.
Audio request. Decoder asserts AREQUEST to indicate that the audio input buffer has
available space. (Not used.)
Ground for core logic and I/O signals.
In synchronous mode, Video data acknowledge. Asserted when DVD data is valid.
Polarity is programmable. In asynchronous mode, data strobing for audio bit stream
input.
2.5-V supply voltage for core logic.
173
174
175
176
177
178
179
180
181
182
183
184
185
186-189
190
191
192
193
194
195
196
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9
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5
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Pin No.
Pin Name
I/O
Description
198
199
200
201
202-204
205
206
207
208
A-DACK
VSS
HOST&SEL
HADDR0-2
DTACKSEL
/CS
R/W
/RD
I
—
I
I
I
I
I
I
Audio data acknowledge.
Ground for core logic and I/O signals.
Pull up.
Host address bus. 3-bit address bus selects one of eight host interface registers.
Tie HIGH to select WAIT signal, LOW to select DTACK signal (Motorola 68K
mode).
Host chip select. Host asserts CS to select the decoder for a read or write operation.
The falling edge of this signal triggers the read or write operation.
Read/write strobe in M mode. write strobe in I mode. Host asserts R/W LOW to select
write and
Read strobe in I mode. Must be held HIGH in M Mode LOW to select Read.
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1-16
17
18-21
22
23-27
28
29
30
31
32
33
34
35
36
37
38
39-45
46
47-52
53-56
57
58
59
60
61
62
63
64
65
66-68
69
70
71
72
73
74
75
76
77
78
79
IC, GDC25D801
Pin No.
Pin Name
I/O
Description
DAT1-16
VSS
ADD1-4
VDD
ADD5-9
X2_MCK
VSS
MCK
VDD
RAS
UCAS
LCAS
WE
OE
SCAN_IN
TEST_SE
TEST_OUT12-6
T_SEL
TEST_OUT5-0
TEST_SEL0-3
TESTSERVO
E_SIN
E_CLK
E_ENB
E_DRB
VSS
SERVO CLK
E_SOUT
VDD
E_ST0-2
GPIO7
GPIO6
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
VSS
SENS
VDD
Bi-directional data to DRAM.
Digital GND.
Address output to DRAM.
Digital power supply.
Address output to DRAM.
Master clock from oscillator for 2x decoding.
Digital GND.
Master clock from oscillator.
Digital power supply.
Row address strobe to DRAM.
Column address upper byte control strobe to DRAM.
Column address lower byte control strobe to DRAM.
Write enable signal to DRAM.
Output enable signal to DRAM.
Scan data input (Not used.)
Test mode selection (low for normal) (Connected to GND.)
Test output (Not used.)
Test selection : 0 for normal.
Test output (Not used.)
Test mode output selection.
TEST PIN (NORMAL STATE = H ) (Connected to VDD.)
SERVO DSP PGM. DOWNLOADING DATA INPUT.
SERVO DSP PGM. DOWNLOADING CLK.
SERVO DSP DOWNLOADING ENABLE.
SERVO DSP PGM. DOWNLOADING DIRECTION.
Digital GND.
SERVO DSP CLOCK INPUT.
SERVO DSP PGM. DOWNLOADING DATA OUTPUT.
Digital power supply.
SERVO DSP DOWNLOADING STATUS 0-2.
SERVO DSP GENERAL I/O: FSON (FOCUS OK INVERTING).
SERVO DSP GENERAL I/O: PSEL.
SERVO DSP GENERAL I/O: ADADDR3 (Not used.)
SERVO DSP GENERAL I/O: FKRST (Not used.)
SERVO DSP GENERAL I/O: FKSET (Not used.)
SERVO DSP GENERAL I/O: FEL (Not used.)
SERVO DSP GENERAL I/O.
SERVO DSP GENERAL I/O: DSP_SENSE.
Digital GND.
SERVO DSP INTERNAL STATUS MONITOR.
Digital power supply.
I/O
—
O
I
O
I
—
I
—
O
O
O
O
O
I
I
O
I
O
I
I
I
I
I
I
—
I
O
—
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
—
O
—
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Pin No.
Pin Name
I/O
Description
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106-111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
Serial Command CLOCK.
Serial Command DATA.
Serial Command LATCH.
TDF.
TDF.
Analog power supply for ADC.
TDF.
Analog GND for ADC.
TDF.
TDF.
Digital GND for ADC.
TDF (Connected to VREF.)
Digital power supply for ADC.
Analog GND for ADC.
TDF.
TDF.
TDF (Connected to VREF.)
Analog GND for ADC.
TDF (Connected to VREF.)
TDF.
Analog power supply for ADC.
TDF.
TDF.
TDF.
TDF (Connected to VREF.)
PLL clock output.
ADC data input (Not used.)
EFMDATA INPUT SELECTION (Connected to GND.)
SUB DATA REQUEST INPUT (Not used.)
SUB Q DATA REQUEST.
5.6448 MHz (DIGITAL OUT CLOCK) (Not used.)
CD DIGITAL DATA OUTPUT (Not used.)
Digital power supply.
SUB Q DATA OUTPUT.
Digital GND.
PWM CHANNEL1 (x3 CARRIER).
PWM CHANNEL1 (x3 CARRIER).
PWM CHANNEL1 (x3 CARRIER): SLED DRIVE OUTPUT.
PWM CHANNEL1 (x1 CARRIER): PDO_CTR PWM OUTPUT.
PWM CHANNEL1 (x1 CARRIER): RF_GAIN_CTL PWM OUTPUT.
PWM CHANNEL1 (x1 CARRIER): TE_BAL_CTL PWM OUTPUT.
SCLK
SDATA
XLAT
AOUT1
AOUT2
AVDD
VCM
AGND
AOUT3
AOUT4
DGND
RFVCM
DVDD
AGND
VREFN
VREFP
INP
AGND
AIN4
AIN3
AVDD
AIN2
AIN1
AIN0
ADCVCM
SCK
EXT_AD0-5
SELEFM
EXCK
SQCK
C16M
DOTX
VDD
SQSO
VSS
PWMCH1
PWMCH2
PWMCH3
PWMCH4
PWMCH5
PWMCH6
I
I
I
O
O
—
I
—
O
O
—
I
—
—
I
I
I
—
I
I
—
I
I
I
I
O
I
I
I
I
O
O
—
O
—
O
O
O
O
O
O
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9
2
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9
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2
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8
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5
1
5
1
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6
7
3
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Pin No.
Pin Name
I/O
Description
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147-154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
EXTERNAL DEFECT INPUT PIN.
SLED ENCODER1 INPUT.
SLED ENCODER2 INPUT (Connected to GND.)
TRACK CROSS PULSE 2 INPUT.
TRACK CROSS PULSE 1 INPUT.
SERVO DSP INTENAL STATUS SERIAL OUTPUT.
INTERNAL GENERATED FOK (Focus OK) H=OK.
Digital power supply.
INTERNAL GENERATED DEFECT: H=DEFECT.
Digital GND.
SLD_FG=(SL_ENC1) XOR (SL_ENC2) (Not used.)
TRACK CROSS PULSE.
TRACK CROSS MONITOR (Not used.)
SERVO DSP INTERRUPT 1 MONITOR (MICOM COMMAND INT) (Not used.)
SERVO DSP INTERRUPT 2 MONITOR (FOCUS SERVO INT) (Not used.)
Digital GND.
SERVO DSP INTERRUPT 1 MONITOR (TRACK SERVO INT) (Not used.)
SERVO DSP INTERRUPT 1 MONITOR (Not used.)
Digital power supply.
A/D 7824 OUTPUT ENABLE (LOW ACTIVE) (Not used.)
A/D 7824 A/D CONVERTER A/D CONVERSION END STATUS (Not used.)
A/D 7824 A/D CONVERTER DATA BUS0-7. (Connected to GND.)
A/D 7824 A/D CONVERTER ADDRESS (Not used.)
Digital power supply for ADC.
A/D 7824 A/D CONVERTER ADDRESS (Not used.)
Digital GND for ADC.
Analog GND for ADC.
TDF.
Analog power supply for ADC.
TDF.
TDF.
TDF.
Spindle motor control signal (Not used.)
Spindle motor control signal (Not used.)
Not used.
Spindle motor ON/OFF control signal.
CLV servo lock signal.
TDF.
Digital GND.
SCAN DATA OUTPUT (Not used.)
Digital power supply.
DEFECT_IN_A
SI_ENC1
SI_ENC2
TZC
MIRR
MSDATAO
FOK
VDD
DEFECT
VSS
SLD_FG
C_SIG
COMP
INT1_
INT2_
VSS
INT3_
INT4_
VDD
PADCSB
ADCOMP
VDCDATA0-7
ADADDR0
DVDD
ADADDR1
DGND
AGND
VRT
AVDD
RF
VRM
VRB
MDS
MDP
OVER64
MON
LOCK
FG_M
VSS
SCAN_OUT
VDD
I
I
I
I
I
O
O
—
O
—
O
O
O
O
O
—
O
I
—
I
I
I
O
—
I
—
—
I
—
I
I
I
O
O
O
O
O
I
—
O
—
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Pin No.
Pin Name
I/O
Description
Interrupt request to Host.
Read strobe from HOST.
Write strobe from HOST.
Chip select from HOST.
Internal register address from HOST.
Digital GND.
Bi-directional data to HOST.
Digital power supply.
Bi-directional data to Host.
HARDWARE RESET.
Data request from DIVX module.
Data request from MPEG.
MPEG data.
MPEG data valid signal (low for valid).
MPEG data transfer clock.
MPEG data error detection signal (low indicates error occurred).
MPEG data sector sync. signal.
174
175
176
177
178-183
184
185
186
187-193
194
195
196
197-204
205
206
207
208
INT
RN
WN
CS
A0-5
VSS
PS0
VDD
PS1-7
RESET
REQ_DIVX
REQ_MPEG
MPEG1-8
SENB
SDCLK
SERR
SYNC
O
I
I
I
I
—
I
—
I/O
I
I
I
O
O
O
O
O
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9
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8
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5
1
5
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1
2
3
4-11
12
13, 14
15
16-21
22
23-30
31
32-39
40
41, 42
43
44-47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
IC, HD6417034AFI20
Pin No.
Pin Name
I/O
Description
Z06
DSP_INT
GND
D00-D07
GND
D08, D09
VCC
D10-D15
GND
A00-A07
GND
A08-A15
GND
A16, A17
VCC
A18-A21
/ROM_CS
/CASH
/IOCS1
/CASL
GND
BCA_CODE
/RAS
DPLL_L
/MICOM_WAIT
/WR
E_SOUT
/RD
DSP_SENSE
GND
E_SIN
E_CLK
MPEG_WR
M_REQ
I/O
I/O
I
I/O
I
I/O
I
I/O
I
O
I
O
I
O
I
O
O
O
O
O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I/O
I/O
I/O
I/O
SUB Q Code Sync Detection Signal (CD Disc Mode).
1. Interrupt request signal to µ-COM (DVD disc mode).
2. Type: a. Track miss occurred
b. Search End
c. New sector out start
d. DSI data is ready
e. New sector in
f. System data is ready
g. Back track jump request
GND.
Data Line 00-07.
GND.
Data Line 08, 09.
5VD.
Data Line 10-15.
GND.
Address Line 00-07.
GND.
Address Line 08-15.
GND.
Address Line 16, 17.
5VD.
Address Line 18-21.
Chip Enable For Flash ROM.
CAS for Higher Byte for DRAM.
Chip Enable to Multiplexer (IC101).
CAS for Lower Byte for DRAM.
GND.
BCA Code Input when DIVX Disc Mode ™ Not used.
RAS for DRAM.
Digital PLL IC Serial Data Latch Out.
MPEG IC Internal Status Serial Input.
Write Signal for DRAM/FlashROM/DSP/MPEG.
Servo DSP Program Downloading Data Out.
Read Signal for DRAM/FlashROM/DSP/MPEG.
Command response signal (SERVO/DSP ™ µ-COM).
GND.
Servo DSP Program Downloading Data IN.
Servo DSP Program Downloading Clock.
MPEG and Host I/F Read/Write Control Output.
Serial Communication Request to Front µ-COM.
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Pin No.
Pin Name
I/O
Description
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81, 82
83-85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
F_REQ
/STROBE
SENS_MCOM
MPEG_INT
VCC
NC
GND
X1
X2
VCC
NC
VCC
NC
MICOM_RESET
VCC
GND
VCC
VCC
SBADD
ECHO
MIC_A
DISC_A
GND
F/R
LOCK
DEFECT
FOK
GND
IIC_DATA
IIC_CLK
VCC
LOAD_FR
MSDATA0
S_DATA
S_CLK
SLD_FG
SPINDLE_FG
I/O
I/O
I/O
I/O
I
—
I
I
O
I
—
I
—
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I/O
I/O
I
I/O
I/O
I/O
I/O
I/O
I/O
Serial Communication Request from Front µ-COM.
Flash ROM Download I/F (Data Strobe in).
1. Servo Event detection signal input
2. Type: a. Focus Error S-curve detection
b. 1 track jump completed
c. 10 track jump completed
d. etc
Interrupt Input from MPEG (IC301).
5VD.
NC.
GND.
Crystal (20MHz) Input.
Crystal (20MHz) Output.
5VD.
NC.
Low Active Reset Input from Front.
5VD.
GND.
5VD.
3.3VD.
SBADD (Sub Beam Add) Signal Input from RF IC ™ Not used.
DC voltage of Echo Volume Input.
Mic Audio Signal Input for Karaoke Score Function ™ Not used.
Disc Audio Signal Input for Karaoke Score Function ™ Not used.
GND.
Spindle Rotation direction Input from Spindle Motor IC.
CLV Servo Locking Signal Input from DSP IC.
DISC DEFECT DETECTION Signal Input (Active High).
FOCUS OK signal (H=OK) from DSP.
GND.
IIC Bus Data for EEPROM (IC114) and Video ENCODER.
IIC Bus Clock for EEPROM (IC114) and Video ENCODER.
5VD.
Tray Open and Close Control output.
Servo DSP IC Internal Status Serial Input.
Serial command interface port between RF or SERVO/DSP IC and µ-COM.
Sled Motor FG Input.
Input the FG Signal of Spindle Motor.
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5
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Pin No.
Pin Name
I/O
Description
106
107
108
109
110
111
112
GND
RXDO
TXDO
SQSO
MODE_SW
SCKO
SQCK
I
I/O
I/O
I/O
I/O
I/O
I/O
GND.
Serial Data Input from Front.
Serial Data OUT to Front.
SUB Q Data Input from Servo & DSP IC.
Program Download mode detect (Download mode is “L”).
Serial Interface Clock to Front.
SUB Q Data Request to Servo & DSP IC.
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5
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5
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75
1
2
3
4
5
6
7
8
9
10
11
12
13
14, 15
16
17-20
21
22
23
24
25-31
32-40
41
42
43-52
53-56
57
58
59
60-64
65
66
67
68-70
71
72
73
74
75
76
77
IC, LC866112B-5N21
Pin No.
Pin Name
I/O
Description
P35
P36
P37
PWM1
TEST1
/RES
XT1
XT2
VSS
CF1
CF2
VDD
P80
P81, P82
P83
P84-P87
MODE_SW
M_REQ
P72
P73
G1-G7
P1-P9
VPP
VKK
P10-P19
S26-S29
S30
S31
P00
P01-P05
ZOOM_RST
V07
VSS
P10-P12
F_RXD
F_TXD
F_CLK
F_REQ
M_RESET
PWR_CTL
P31
I
I
I
O
—
I
I
O
—
I
O
—
I
I
I
I
I/O
I
I
I
O
O
I
I
O
—
—
—
—
—
I/O
—
—
—
O
I
I
O
O
O
I/O
Select down SW input from CN505 (SW509).
Enter SW input from SW501.
Select right SW input CN505 (SW509).
Not used.
Not used (Test port).
Reset signal input from IC501 3 pin.
Not used (Input for 32.768kHz crystal oscillation).
Not used (Output for 32.768kHz crystal oscillation).
GND.
Ceramic resonator X501 (6MHz) oscillation input.
Ceramic resonator X501 (6MHz) oscillation output.
VCC (5V).
KEY IN input from CN504.
Reserved.
Shuttle 3 line A/D input.
Not used.
“LOW” at program download mode.
Request signal (Active “LOW”) from IC108 (Main µ-COM, SH7034).
Not used.
Remocon receiver signal input.
VFD display control signal output. DIG 501 G1 to G7.
VFD display control signal output. DIG 501 P1 to P9.
VCC (5VAU).
-27V from CN503 (SMPS).
VFD display control signal output. DIG 501 P10 to P19.
Not used.
D503 option (Present at AIWA remocon model).
Not used.
Diode option input.
Not used.
GND.
Reserved.
Serial data to IC108 (Main µ-COM, SH7034).
Serial data input from IC108 (Main µ-COM, SH7034).
Serial clock input from IC108 (Main µ-COM, SH7034).
Request signal (Active “LOW”) to IC108 (Main µ-COM, SH7034).
Reset signal (Active “LOW”) to IC108 (Main µ-COM, SH7034).
Power control (Active “HIGH”) to main board.
Not used.
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P32
P33
P34
Pin No.
Pin Name
I/O
Description
78
79
80
I
I
I
UP signal input from CN505 (SW509).
JOG signal “JSW1” input CN505 (JS500).
LEFT signal input from CN505 (SW509).
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1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28-30
31
32
33
34
35
36
37
38
39-43
44
IC, XC9536-15VQ44C
Pin No.
Pin Name
I/O
Description
SCART1
SCART2
TEST PIN
GND
PWR_CTL
TEST PIN
MPEG_CS
DSP_CS
TD1
TMS
TCK
PP_CS
CLOSE_SW
OPEN_SW
VCC
SENSE
GND
ZISERR
DAC_LO
DINO_CS
WR
MICOM_WAIT
MIC_ON
TDO1
GND
VCC
RF_LAT
A21-A19
MPEG_WAIT
LIMIT_SW
MICOM_RESET
EXP_W2
VCC
PWR_CTL
MPEG_ERROR
SENSE_MCOM
DO0-DO4
IOCS1
O
O
O
—
O
O
O
O
I
I
I
O
I
I
—
I
—
I
O
O
I
O
I
O
—
—
O
I
I
I
I
O
—
I
O
O
I/O
I
Wide disc playback high output (16:9 mode detect).
DVD power on HIGH (HIGH signal output to SCART 8 pin, SCART enable).
For software debugging.
Ground.
Power control output to expander IC.
For software debugging.
IC301 (MPEG IC, ZIBA-3) chip select.
IC206 (DSP IC, GDC25D801) chip select.
JTAG program port for CPLD upgrade.
Software download adapter select.
Tray limit SW input (LOW is input at tray close end position).
Tray limit SW input (LOW is input at tray open end position).
VCC.
Interface signal for IC206 (DSP IC, GDC25D801).
Ground.
EDC (Error detection & correction) signal input from IC206 (DSP IC, GDC25D801).
Audio DAC latch strobe signal.
Not used.
IC108 (Main µ-COM, SH7034) bus write signal.
µ-COM WAIT signal.
Karaoke MIC input.
JTAG program port for CPLD Upgrade.
Ground.
VCC.
IC201 (RF IC, TA1254) serial interface latch signal.
IC108 (Main µ-COM, SH7034) address signal.
Wait signal from IC301. (MPEG IC, ZIBA-3)
Sled limit switch input.
µ-COM, expander reset signal input.
IC103 (Expander, 74HC374) latch strobe.
VCC.
Power control input from IC500 (Front µ-COM).
EDC (Error detection & correction) signal output to IC301 (MPEG IC, ZIBA-3).
IC206 (DSP IC, GDC25D801) interface signal to IC108 (Main µ-COM, SH7034).
IC108 (Main µ-COM, SH7034) data bus.
IC101 (CPLD, XC9536) chip select from IC108 (Main µ-COM, SH7034).
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IC BLOCK DIAGRAM
IC, BA5983FP
IC, BA6859AFP
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IC, PLL1700E
IC, KIA393F
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IC, TA1254F
IC, SN74AHC374PWLE
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0
5
1
5
1
3
6
7
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82
81
MECHANICAL EXPLODED VIEW 1/1
463
452
462
250
464
462
462
462
463
463
463
452
283
463
280
463
452
463
463
463
300
452
LDM-H109
MAIN CHASSIS
ASSY
P.C.B
P.C.B
P.C.B
P.C.B
P.C.B
REF. NO
PART NO.
KANRI
DESCRIPTION
NO.
MECHANICAL PARTS LIST 1/1
Basic color symbol
Color
Basic color symbol
Color
Basic color symbol
Color
B
Black
C
Cream
D
Orange
G
Green
H
Gray
L
Blue
LT
Transparent Blue
N
Gold
P
Pink
R
Red
S
Silver
ST
Titan Silver
T
Brown
V
Violet
W
White
WT
Transparent White
Y
Yellow
YT
Transparent Yellow
LM
Metallic Blue
LL
Light Blue
GT
Transparent Green
LD
Dark Blue
DT
Transparent Orange
COLOR NAME TABLE
250 S1-10R-014-3A0 CASE TOP
280 S7-21R-F12-5A0 DVD-2520N EVNT PANE
283 S5-81R-000-7A0 TRAY DOOR ASSY
300 S4-10R-AHC-02B NI NM CORE SP-2 1 POW
452 S3-530-51A-000 SCREW,SPECIAL
462 S3-530-46K-000 SPECIAL SCREW 3-10
463 S3-530-51B-000 SPECIAL SCREW
464 S3-530-46N-000 SPECIAL SCREW 3-8
w w w
.
x i a o y u 1 6 3 .
c o m
Q Q
3 7 6 3 1 5 1 5 0
9
9
2
8
9
4
2
9
8
T E L
1 3 9 4 2 2 9 6 5 1 3
9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
Q
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84
83
MECHANISM EXPLODED VIEW 1/1
040
038
427
041
PU BASE
037
039
031
035
428
418
418
004
018
013
014
015
016
017
026
419
418
418
019
418
418
418
418
MAIN BASE
A02
011
A06
P.C.B
423
012
w w w
.
x i a o y u 1 6 3 .
c o m
Q Q
3 7 6 3 1 5 1 5 0
9
9
2
8
9
4
2
9
8
T E L
1 3 9 4 2 2 9 6 5 1 3
9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
Q
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85
REF. NO
PART NO.
KANRI
DESCRIPTION
NO.
MECHANISM PARTS LIST 1/1
004 S8-10H-105-5A0 CLAMP,LDM-R608 BRACKET
011 S2-10H-101-1A0 FRAME UP/DOWN
012 S0-40H-103-9A0 RUBBER
013 S4-00H-101-0A0 LOADING BELT
014 S4-70H-112-9A0 PULLEY GEAR
015 S6-81R-102-1A0 LOADING MOTOR ASSY
016 S4-70H-113-1A0 LOADING GEAR
017 S4-30H-000-4A0 LOADING CAM
018 S4-70H-113-0A0 EMERGENCY GEAR
019 S9-31H-000-3A0 HOLDER ASSY DECK ON
026 S3-90H-102-1A0 DISC TRAY
031 S3-70H-108-5B0 SHAFT PU SUB
035 S3-70H-108-5A0 SHAFT PU MAIN
037 S6-80H-B10-24B MOTOR(MECH)
038 S9-70H-110-0A0 SPRING SKEW
039 S3-71H-100-9A0 LEAD SCREW SHAFT
040 S6-81H-102-0A0 PU FEED MOTOR ASSY
041 S0-40H-104-0A0 RUBBER
428 SS-ZZH-101-6A0 SCREW,+2.0-3.5
A02 S8-61H-001-1A0 DISC CLAMP ASSY
A06 S4-05H-108-0B0 MECHANISM ASSY
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5
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TEL 13942296513 QQ 376315150 892498299
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931196
Printed in Singapore
2–11, IKENOHATA 1–CHOME, TAITO-KU, TOKYO 110-8710, JAPAN TEL:03 (3827) 3111
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' |
| related |
array (
8 =>
array (
'id' => '8',
'pid' => '5',
'pids' => '0,5',
'name' => '电子电工',
'dirname' => 'dzdg',
'pdirname' => 'hangye/',
'child' => 0,
'disabled' => '0',
'ismain' => 1,
'childids' => 8,
'thumb' => '',
'show' => '1',
'setting' =>
array (
'disabled' => '0',
'linkurl' => '',
'getchild' => '0',
'notedit' => '0',
'seo' =>
array (
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'template' =>
array (
'pagesize' => '20',
'mpagesize' => '20',
'list' => 'list.html',
'category' => 'category.html',
'search' => 'search.html',
'show' => 'show.html',
),
'cat_field' => NULL,
'module_field' => NULL,
'urlrule' => 4,
'html' => 0,
'chtml' => 0,
),
'displayorder' => '0',
'icon' => '',
'index' => '2',
'mid' => 'wenku',
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array (
0 => '8',
),
'is_post' => 1,
'tid' => 1,
'url' => 'http://www.wenhuiw.com/wenku/dzdg',
'total' => '请使用count标签查询',
'field' =>
array (
),
),
12 =>
array (
'id' => '12',
'pid' => '5',
'pids' => '0,5',
'name' => '电脑手机',
'dirname' => 'dnsj',
'pdirname' => 'hangye/',
'child' => 0,
'disabled' => '0',
'ismain' => 1,
'childids' => 12,
'thumb' => '',
'show' => '1',
'setting' =>
array (
'disabled' => '0',
'linkurl' => '',
'getchild' => '0',
'notedit' => '0',
'seo' =>
array (
),
'template' =>
array (
'pagesize' => '20',
'mpagesize' => '20',
'list' => 'list.html',
'category' => 'category.html',
'search' => 'search.html',
'show' => 'show.html',
),
'cat_field' => NULL,
'module_field' => NULL,
'urlrule' => 4,
'html' => 0,
'chtml' => 0,
),
'displayorder' => '0',
'icon' => '',
'index' => '2',
'mid' => 'wenku',
'pcatpost' => 0,
'topid' => '5',
'catids' =>
array (
0 => '12',
),
'is_post' => 1,
'tid' => 1,
'url' => 'http://www.wenhuiw.com/wenku/dnsj',
'total' => '请使用count标签查询',
'field' =>
array (
),
),
13 =>
array (
'id' => '13',
'pid' => '5',
'pids' => '0,5',
'name' => '交通道路',
'dirname' => 'jtdl',
'pdirname' => 'hangye/',
'child' => 0,
'disabled' => '0',
'ismain' => 1,
'childids' => 13,
'thumb' => '',
'show' => '1',
'setting' =>
array (
'disabled' => '0',
'linkurl' => '',
'getchild' => '0',
'notedit' => '0',
'seo' =>
array (
),
'template' =>
array (
'pagesize' => '20',
'mpagesize' => '20',
'list' => 'list.html',
'category' => 'category.html',
'search' => 'search.html',
'show' => 'show.html',
),
'cat_field' => NULL,
'module_field' => NULL,
'urlrule' => 4,
'html' => 0,
'chtml' => 0,
),
'displayorder' => '0',
'icon' => '',
'index' => '2',
'mid' => 'wenku',
'pcatpost' => 0,
'topid' => '5',
'catids' =>
array (
0 => '13',
),
'is_post' => 1,
'tid' => 1,
'url' => 'http://www.wenhuiw.com/wenku/jtdl',
'total' => '请使用count标签查询',
'field' =>
array (
),
),
14 =>
array (
'id' => '14',
'pid' => '5',
'pids' => '0,5',
'name' => '机械设备',
'dirname' => 'jixie',
'pdirname' => 'hangye/',
'child' => 0,
'disabled' => '0',
'ismain' => 1,
'childids' => 14,
'thumb' => '',
'show' => '1',
'setting' =>
array (
'disabled' => '0',
'linkurl' => '',
'getchild' => '0',
'notedit' => '0',
'seo' =>
array (
),
'template' =>
array (
'pagesize' => '20',
'mpagesize' => '20',
'list' => 'list.html',
'category' => 'category.html',
'search' => 'search.html',
'show' => 'show.html',
),
'cat_field' => NULL,
'module_field' => NULL,
'urlrule' => 4,
'html' => 0,
'chtml' => 0,
),
'displayorder' => '0',
'icon' => '',
'index' => '2',
'mid' => 'wenku',
'pcatpost' => 0,
'topid' => '5',
'catids' =>
array (
0 => '14',
),
'is_post' => 1,
'tid' => 1,
'url' => 'http://www.wenhuiw.com/wenku/jixie',
'total' => '请使用count标签查询',
'field' =>
array (
),
),
15 =>
array (
'id' => '15',
'pid' => '5',
'pids' => '0,5',
'name' => '能源动力',
'dirname' => 'nydl',
'pdirname' => 'hangye/',
'child' => 0,
'disabled' => '0',
'ismain' => 1,
'childids' => 15,
'thumb' => '',
'show' => '1',
'setting' =>
array (
'disabled' => '0',
'linkurl' => '',
'getchild' => '0',
'notedit' => '0',
'seo' =>
array (
),
'template' =>
array (
'pagesize' => '20',
'mpagesize' => '20',
'list' => 'list.html',
'category' => 'category.html',
'search' => 'search.html',
'show' => 'show.html',
),
'cat_field' => NULL,
'module_field' => NULL,
'urlrule' => 4,
'html' => 0,
'chtml' => 0,
),
'displayorder' => '0',
'icon' => '',
'index' => '2',
'mid' => 'wenku',
'pcatpost' => 0,
'topid' => '5',
'catids' =>
array (
0 => '15',
),
'is_post' => 1,
'tid' => 1,
'url' => 'http://www.wenhuiw.com/wenku/nydl',
'total' => '请使用count标签查询',
'field' =>
array (
),
),
16 =>
array (
'id' => '16',
'pid' => '5',
'pids' => '0,5',
'name' => '电气工控',
'dirname' => 'dqgk',
'pdirname' => 'hangye/',
'child' => 0,
'disabled' => '0',
'ismain' => 1,
'childids' => 16,
'thumb' => '',
'show' => '1',
'setting' =>
array (
'disabled' => '0',
'linkurl' => '',
'getchild' => '0',
'notedit' => '0',
'seo' =>
array (
),
'template' =>
array (
'pagesize' => '20',
'mpagesize' => '20',
'list' => 'list.html',
'category' => 'category.html',
'search' => 'search.html',
'show' => 'show.html',
),
'cat_field' => NULL,
'module_field' => NULL,
'urlrule' => 4,
'html' => 0,
'chtml' => 0,
),
'displayorder' => '0',
'icon' => '',
'index' => '2',
'mid' => 'wenku',
'pcatpost' => 0,
'topid' => '5',
'catids' =>
array (
0 => '16',
),
'is_post' => 1,
'tid' => 1,
'url' => 'http://www.wenhuiw.com/wenku/dqgk',
'total' => '请使用count标签查询',
'field' =>
array (
),
),
) |
