S5L9294 9226 VCD原理图

1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 A B C D 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 D C B A Title Number Revision Size A1 Date: 2 3 - J u l - 2 0 0 5 Sheet of File: D : \ S P C A 7 \ 7 7 8 \ 7 7 6 . d d b Drawn By: ROM_D0 ROM_D7 ROM_A17 ROM_A6 ROM_A4 ROM_A0 ROM_D5 ROM_A14 ROM_A7 ROM_A5 ROM_A9 VBIAS ROM_D2 FSADJ ROM_A15 ROM_A1 CVBS ROM_A12 ROM_A8 ROM_A16 ROM_A2 ROM_D6 ROM_A13 ROM_D3 ROM_D1 ROM_D4 ROM_A11 ROM_A3 ROM_A10 COMP SCK SI SO SYNC 9226_RESET 9226_MDATA 9226_MCLK 9226_ISTAT 9226_MLT LOUT VC ROUT EFMI LOCK GPIO37 SMEF SMDP SMDS WDCK MIC_VM MIC_ATO MIC_AIN RAM_D6 RAM_D7 RAM_CLK RAM_D8 RAM_D9 RAM_D10 RAM_D11 RAM_D12 RAM_D13 RAM_D0 RAM_D1 RAM_D2 RAM_D3 RAM_D4 RAM_D5 MIC_VRB RAM_D14 RAM_D15 RAM_A0 RAM_A1 RAM_A2 RAM_BA1 RAM_A8 RAM_A9 RAM_A10 RAM_A11 RAM_BA0 RAM_RAS RAM_CAS RAM_WE CLKIO_1 RAM_A3 RAM_A4 RAM_A5 RAM_A7 RAM_A6 CLKIN_1 RAM_DQM0 VREFIN VHALF EFMI PAD0 WDCK SMEF 9226_MDATA SMDP 9226_MLT 9226_MCLK SMDS 9226_RESET 2SPEED LOCK S M O N 9226_ISTAT GUNIO ROUT LOUT 2SPEED GPIO37 PAD1 ROM_A2 RAM_D15 ROM_D2 ROM_A18 ROM_A17 ROM_A0 ROM_A6 RAM_A5 RAM_D10 ROM_A7 ROM_D5 RAM_D3 ROM_A14 ROM_A3 RAM_A8 RAM_D11 ROM_D4 RAM_A9 RAM_D13 ROM_D1 ROM_A10 ROM_A5 ROM_A1 ROM_A4 RAM_D7 RAM_A3 RAM_D1 ROM_D7 RAM_D0 RAM_D14 RAM_A1 ROM_D6 RAM_A0 ROM_A16 RAM_D6 RAM_D9 ROM_D3 RAM_D5 ROM_A8 ROM_A15 RAM_A4 ROM_A13 ROM_A9 ROM_A11 RAM_A11 RAM_A2 ROM_D0 ROM_A12 RAM_D4 RAM_D12 RAM_D2 RAM_D8 RAM_A7 RAM_A6 RAM_A10 LOCK 9226_ISTAT FEIN 9226_MDATA SP+ WDCK PDBD PD1 9226_RESET PDAC F+ SL- LOAD+ LD1 PDE EFMI M + SLIN M - SMDP SL- VR PD2 CLOSE SP- F- SPIN 9226_MCLK LOAD- PD LD1 SL+ SL+ LIMSW SPIN LD2 SMDS TEIN 9226_MLT PDF SLIN OPEN 2SPEED PD SMEF FEIN E TEIN ROUT LOUT RESET LIMSW GND AGND AUD_GND V_GND MICGND VGND VID_GND MIC_GND E B C D A F PD VR LD1 T- T+ F+ T+ T- F- F SP+ SP- R 5 3 1 2 0 K R30 12K R8 1 0 0 E C42 103 C9 0 . 1 U 1 2 D1 5V6 R 5 2 1 2 0 K C 5 5 0 . 1 U R3 4 . 7 K C 5 4 0 . 1 U C30 104 R34 10K C24 0.15 RFM 1 RFO 2 EQI 3 EQO 4 E F M 5 VCC 6 FRSH 7 FSET 8 FLB 9 FGD 10 FSI 11 TGU 12 ISTAT 1 3 MCK 1 4 MDATA 1 5 MLT 1 6 RESET 1 7 CLV1 1 8 WDCK 1 9 LOCK 2 0 E F M 2 1 ASY 2 2 S P M 2 3 SPO 2 4 S L M 25 SLO 26 S L P 27 TEM 28 TEO 29 F E M 30 FEO 31 GND 32 TZC/SSTOP 33 TEIO 34 LPFT 35 ATSC 36 LD 3 7 PD 3 8 PDAC 3 9 PDBD 4 0 PDF 4 1 PDE 4 2 DCB 4 3 MCP 4 4 DCCI 4 5 DCCO 4 6 VREF 4 7 EQC 4 8 U4 S 1 L 9 2 2 6 C 1 8 1 0 4 + CD3 1 0 U C 1 5 1 0 P C7 0 . 1 U C 3 4 4 7 4 OPEN 1 GND 2 CLOSE 3 CN4 C 3 2 4 7 4 C 5 9 1 0 4 + CD2 1 0 U C3 0 . 1 U XT1 27MHz C 3 5 1 0 2 C 4 0 1 0 3 C 6 0 1 0 2 R 4 5 2 R 2 C51 NC C 6 5 1 0 3 C 5 8 1 0 4 C2 0 . 1 U C 1 6 1 0 0 P R36 820K R 4 1 4 7 K C 1 0 0 . 1 U C 1 9 3 3 P R14 220K +CD5 4 7 U R11 100K + CD10 4 7 U C 5 6 0 . 1 U C29 333 + CD13 4 7 U T- 1 T+ 2 TE_IN 3 D 0 1 . 2 4 REG 5 RE0 6 MUTE 7 GND 8 CLOSE 9 SP_IN 1 0 S P + 1 1 SP- 1 2 GND 1 3 OPEN 1 4 M- 1 5 M + 1 6 F- 1 7 F + 1 8 FE_IN 1 9 D 0 3 . 2 2 0 VCC 2 1 VCC 2 2 VREF 2 3 D4.1 2 4 SL_IN 2 5 SL+ 2 6 SL- 2 7 GND 2 8 U5 K A 9 2 5 9 L 3 FB R 4 6 1 0 0 R C 1 7 1 0 4 C 6 6 0 . 1 U R9 56K 1 1 2 2 4 4 3 3 CN2 PART +CD20 2 2 0 U R6 4 7 0 E A0 1 2 A1 1 1 A2 1 0 A3 9 A4 8 A5 7 A6 6 A7 5 A8 2 7 A9 2 6 A 1 0 2 3 A 1 1 2 5 A 1 2 4 A 1 3 2 8 A 1 4 2 9 A 1 5 3 A 1 6 2 A 1 7 3 0 A 1 8 3 1 A 1 9 1 D0 1 3 D1 1 4 D2 1 5 D3 1 7 D4 1 8 D5 1 9 D6 2 0 D7 2 1 VCC 3 2 GND 1 6 CE 2 2 OE 2 4 U2 SST37VF020-PLCC C 6 4 1 0 2 1 2 D2 LED C 4 1 1 0 4 C 5 2 0 . 1 U C 1 4 0 . 1 U C26 0.1 2 1 3 Q3 9 0 1 4 C 6 1 1 0 3 C 2 2 0 . 1 U R 1 7 8 2 K C 2 1 0 . 1 U R 2 1 0 E R35 220E R 4 7 3 9 0 E C 2 0 0 . 1 U C 5 3 0 . 1 U C43 102 8 8 9 9 1 0 1 0 1 1 1 1 1 2 1 2 1 3 1 3 1 5 1 5 1 6 1 6 1 7 1 7 1 8 1 8 1 9 1 9 2 0 2 0 2 1 2 1 2 2 2 2 7 7 6 6 5 5 4 4 3 3 2 2 1 1 1 4 1 4 2 3 2 3 2 4 2 4 2 5 2 5 C0N-22 + CD1 1 0 U R 2 8 8K2 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 CN5 F F C 1 7 R5 3 3 K R38 100K R16 120K C8 0 . 1 U R1 2 R 2 R31 1M C45 0.1U R 1 0 1 2 0 K 1 2 D3 LED R 4 2 2 R 2 C 1 2 0 . 1 U R 5 4 2 K R33 220K A0 2 3 A1 2 4 A2 2 5 A3 2 6 A4 2 9 A5 3 0 A6 3 1 A7 3 2 A8 3 3 A9 3 4 CAS 1 7 RAS 1 8 LDQM 1 5 WE 1 6 CS 1 9 CKE 3 7 CLK 3 8 UDQM 3 9 D0 2 D1 4 D2 5 D3 7 D4 8 D5 1 0 D6 1 1 D7 1 3 D8 4 2 D9 4 4 D 1 0 4 5 D 1 1 4 7 D 1 2 4 8 D 1 3 5 0 D 1 4 5 1 D 1 5 5 3 NC 3 6 BA0 2 0 VDD 1 VDD 27 VSS 28 VSS 41 A10/AP 2 2 NC/RFU 4 0 VDDq 3 VDDq 9 VDDq 43 VDDq 49 VSSQ 6 VSSQ 12 VSSQ 46 VSSQ 52 A 1 1 3 5 BA1 2 1 VSS 54 VDD 14 U3 4 M x 1 6 ( S 4 0 3 0 C ) R 2 3 2 2 0 K C 3 7 1 0 3 + CD8 4 7 U C1 1 0 4 R 1 8 1 0 E R2 6 8 E C4 0 . 1 U C 3 8 4 7 4 C25 391 R 4 0 4 R 7 C 2 7 0 . 0 6 8 R 1 3 4 7 K C 3 3 1 0 2 C 6 2 0 . 1 U C 4 9 1 0 1 + CD16 1 0 U F +CD17 4 7 U + CD6 4U7 R 4 3 4 7 K C44 0.1U C48 103 + CD15 2 2 0 U C 1 3 0 . 1 U R 3 7 2 2 E C 5 7 0 . 1 U R 2 2 8 2 K 2 1 3 Q2 9 0 1 4 C46 102 L 1 C O I L 1 0 0 U + CD12 1 0 U F +CD19 4 7 U C39 333 C6 0 . 1 U C 3 6 1 0 2 +CD7 4 7 U + CD4 1 0 U +CD11 2 2 0 U C5 0 . 1 U R 2 0 1 0 0 K + CD14 1 0 0 U +CD18 1 0 0 U C63 471 R 2 4 1 0 K C23 0.1 2 1 3 Q1 KTA1266 C47 104 R 2 6 0 E R 5 0 1 2 0 K 1 2 S W 1 S R 5 1 1 2 0 K R49 75E R 4 8 3 3 K R 2 9 8 2 E R32 18K ROM_ADDR5 38 PVDD2 37 PVSS2 36 ROM_ADDR9 3 9 ROM_ADDR13 4 3 ROM_ADDR8 4 1 ROM_ADDR7 4 2 ROM_ADDR6 4 0 ROM_ADDR12 4 4 ROM_ADDR16 4 8 ROM_ADDR17 4 7 ROM_ADDR14 4 5 GPIOA8/ROM_ADDR18 4 9 GPIOA9/ROM_ADDR19 5 0 PVDD1 5 1 HSYNC 5 5 GPIOA11 5 4 GPIOA10 5 3 PVSS1 5 2 VSYNC 5 6 DATA_TV7 5 7 DATA_TV6 5 8 DATA_TV5 5 9 GPIOA13 81 AU_BCK 79 AU_LRCK 78 AU_DATA 77 AU_XCK 76 PVDD3P_1 75 PLL_RESISTOR 74 PVSS3P_1 73 PVDD3P_0 72 PVSS3P_0 71 GPIOA39/PAL_NTSC 70 GPIOA38/CLK27_OUT 69 PVDD2 68 PVSS2 67 GPIOA26/CLKIO 66 CLKIN 65 DATA_TV0 6 4 DATA_TV1 6 3 DATA_TV2 6 2 DATA_TV3 6 1 DATA_TV4 6 0 DA8 12 DA7 13 DA6 14 DA5 15 DA4 16 DA0 17 DA1 18 DA2 19 DA3 20 ROM_DATA3 21 ROM_DATA4 22 ROM_DATA2 23 ROM_DATA5 24 ROM_DATA1 25 ROM_DATA6 26 ROM_DATA0 27 ROM_DATA7 28 ROM_ADDR1 30 ROM_ADDR3 32 ROM_ADDR4 34 ROM_ADDR11 35 PVSS1 7 PVDD1 8 WE_B 9 CAS_B 10 RAS0_B 11 DD11 3 DD10 4 DD9 5 DD8 6 VM 1 0 5 AIN 1 0 6 CD_BLCK 98 PVDD3P_2 1 0 8 PVSS2 100 GPIOA5/DA10 1 1 0 GPIOA4/DA9 1 1 1 GPIOA3/BA0 1 1 2 GPIOA2/DQM1 1 1 3 GPIOA1/DQM0 1 1 4 GPIOA0/RAS1_B/BA1 1 1 5 DD2 1 1 8 PVSS2 1 2 8 DD6 1 2 2 CD_LRCK 97 RESET_B 99 PVDD2 101 GPIOB40/CD_XCK 102 GPIOB41 1 0 3 GPIOA17 85 GPIOA16 84 GPIOA15 83 GPIOA14 82 GPIOA12 80 GPIOA20 88 GPIOA19 87 GPIOA18 86 CD_DATA 96 PVDD1 95 PVSS1 94 GPIOA25 93 GPIOA24 92 GPIOA23 91 GPIOA22 90 GPIOA21 89 P V S S 3 P _ 2 1 0 4 DD3 1 1 9 DD4 1 2 0 DD5 1 2 1 DD15 1 2 4 DD14 1 2 5 DD13 1 2 6 ROM_ADDR0 29 ROM_ADDR2 31 GPIOA6 1 0 9 ROM_ADDR10 33 ROM_ADDR15 4 6 ATO 1 0 7 DD7 1 2 3 GPIOA7/SDRAM_CLK 1 2 7 DD12 2 PVDD2 1 DD0 1 1 6 DD1 1 1 7 U1 S 5 L 9 2 9 4 - 1 2 8 R7 4 . 7 K R 2 7 1 8 K R 2 5 2 2 0 K C 3 1 0 . 0 1 +CD21 4 7 U L 4 FB L 2 FB R12 47K C 1 1 1 0 4 R 1 9 2 2 K +CD9 1 0 0 U C50 151 R4 2 R 2 R 4 4 2 R 2 1 1 2 2 4 4 3 3 CN3 PART C28 222 R 3 9 4K7 R15 22K B PD1 A C PD2 D VCC33 VCC18 GND GND VCC33 GND VVCC3 VGND VGND VVCC3 GND VCC33 GND VCC18 AGND AVCC33 AGND AGND AGND VCC33 GND GND MICGND GND VCC33 MICGND MICVCC GND VCC18 VCC33 VCC18 GND AGND VCC18 GND VCC33 GND GND GND VCC33 VCC33 GND GND VCC33 GND GND VCC33 VCC33 VC AGND VCC AGND VC VCC AGND VCC VC VCC GND 9 V VC VC AGND GND AGND VC AGND 9 V VCC + 3 . 3 V AGND AGND VCC VC AGND VC AGND AGND GND 9 V AUD_GND VVCC3 MIC_GND AUD_GND GND GND VGND AUD_GND GND AVCC33 AUD_GND AUD_GND MICVCC GND VCC18 GND 9 V AUD_GND +3V3 VID_GND GND VID_GND VCC33 VCC33 VCC33 VCC33 VID_GND VCC VC AGND AGND +3V3 VGND VGND + 3 . 3 V AGND DRAM_A[0..10] DRAM_D[0..15] R O M _ A [ 0 . . 1 8 ] ROM_D[0..7] PAD0 WDCK 2SPEED SMDS 9 2 2 6 _ M C L K SMDP S M E F EFMI 9 2 2 6 _ I S T A T SMON LOCK 9226_MDATA 9 2 2 6 _ M L T 9 2 2 6 _ R E S E T GUNIO ROUT LOUT PAD1 ROM_D[0..7] RAM_DQM0 RAM_CAS R O M _ A [ 0 . . 1 8 ] R A M _ A [ 0 . . 1 1 ] RAM_CLK RAM_WE RAM_RAS RAM_BA0 R A M _ D [ 0 . . 1 5 ] RAM_BA1 CD_L CD_R DISC_IN ACC ACC SCK CD_L SYNC RESET CLOSE DISC_IN LOAD+ OPEN SO CD_R SI A_MUTE LOAD- CVBS