5 4 3 2 1 D D C C B B A A YPbPr INTERFACE JAGUAR PANEL INTERFACE SDRAM BASED FRAME BUFFER VER:DIE S2300 DEINTERLACE MICROCONTROLLER 80C32 Start:2005.01.01 PANEL INTERFACE 14 JAGUAR SDRAM SECTION 12 JAGUAR ANALOG INTERFACE VGA CONNECTOR THIS SHEET 13 POWER SUPPLY AND DECAPS AD9883 INTERFACE LCD TV LCD40V8--2300+Jagasm SHEET NO. DESCRIPTION S2300 SDRAM JAGUAR DIGITAL INTERFACE LVDS PANEL INTERFACE 15 Status:Finished 20030319 DVI INTERFACE 16 2 1 8 6 5 9 11 4 10 7 3 DC-DC 17 00 LCD40V8 Custom 1 17 Wednesday, January 26, 2005 Title Size Document Number Rev Date: Sheet of 5 4 3 2 1 D D C C B B A A C539/C542/C545 $4,10u/10V 使用无极性铝电解电容 00 YPbPr_domestic A 2 17 Wednesday, January 26, 2005 Title Size Document Number Rev Date: Sheet of Pr_in Pb_in Y_in Y_in Pb_in Pr_in HD_V 3 HD_Y 3 HD_U 3 Y_in Pr_in Pb_in GND L+5V L+5V GND GND L+5V GND Q11 MMBT2222ALT1 3 1 2 R255 68k FB96 1 2 R256 68k FB88 1 2 R257 1k Q10 MMBT2222ALT1 3 1 2 R252 68k R253 68k R254 1k Q14 MMBT2222ALT1 3 1 2 R249 68k FB95 1 2 R250 68k YCBCR P17 JST-S6B-PH-K 1 2 4 5 3 6 Y Cb GND GND Cr GND R251 1k R261 82 R263 82 R262 82 C539 10u C542 10u C545 10u 5 4 3 2 1 D D C C B B A A TDA9883 TOP 排版时应注意 下面的 层不走线！ P1.6 P1.5 P1.3 INT0/P3.2 P1.4 251定义 00 AD9883 INTERFACE Custom 3 17 Wednesday, January 26, 2005 Title Size Document Number Rev Date: Sheet of DY[0..7] DY1 DY6 DV[0..7] DV0 DV6 DV2 DY0 DY4 DV4 DV7 DY3 DV3 DV5 DV1 DY5 MC_DATA DY2 MC_SCLK DY7 DU0 DU3 DU2 DU7 DU5 DU[0..7] DU6 DU4 DU1 AD_VS AD_VS VSYNC AD_HS SDA_analog SCL_analog S1C S1A V U Y Y S1BB S1CC S1AA U S1B V HSYNC S1A S1AA S1B S1BB S1C S1CC MC_DATA 4,10,15 2300_VS 4 DY[0..7] 4 2300_HS 4 P_CLK 4 MC_SCLK 4,10,15 DV[0..7] 4 DU[0..7] 4 CTRL_SOURCE 10 HD_U 2 HD_V 2 HD_Y 2 2596_on 15,16 SCL_analog 15 REMOT 15 SDA_analog 15 SOG 4 S1B S1A S1C Y U U Y V AD_VS AD_VS REST_Analog 15 P3.4 4,15 INTR_analog 15 P1.4 15 GND GND GND GND GND GND PVDD GND GND GND L+5V 3.3AN GND +5V GND PVDD GND PVDD GND GND GND GND +12V GND GND GND GND GND GND L+5V GND GND GND GND GND GND 3.3V GND GND GND GND GND GND GND GND GND L+5V GND GND GND GND LM1117MPX-5 U38 3 2 1 4 IN OUT GND TAB C7 47pF CX5 CX C175 open C28 0.1u C476 open C571 0.01u L3 0 U37 PIV 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 IN S1A S2A DA S1B S2B DB GND DC S2C S1C DD S2D S1D EN VCC C29 0.1u FB3 1 2 R3 10K C30 0.1u R199 470 R4 4.7K L4 0 L2 0 C22 10u/16v C547 0.1u R200 470 C34 0.1u FB7 1 2 R8 150 R5 0 C23 4.7pF R271 4k7 C32 0.1u R14 4.7K C2 47uF/10V/5x5.4 1 2 RP5 22Rx4 1 8 2 7 3 6 4 5 C19 0.1u C562 0.001u R272 4k7 C33 0.1u RP6 22Rx4 1 8 2 7 3 6 4 5 C21 4.7pF C44 47pF R21 C31 0.1u C1 47uF/6V/5x5.4 1 2 R19 FB90 1 2 C46 C27 0.1u P25 4pin 1 2 3 4 Intr_main# GND 2596_on/light +3.3V C179 open R13 100 C544 0.1u Com port with Analog_board P2 JST-S6B-PH-K 1 2 4 3 5 6 7 8 SCL 2596_ON_ GND SDA I/O1 INT IO IO R20 C20 10u/16v C561 1nF C26 0.1uF R18 C18 1nF L7 1 2 R17 C4 47uF/10V/5x5.4 1 2 L6 1 2 C17 0.1uF C24 10u/16v R10 4k7 C45 C14 1nF R16 R12 100 R11 150 C546 0.1u C541 0.1u C16 1nF L5 1 2 R215 0 C540 0.1u C12 1nF 9332-9883 P1 JST-S8B-PH-K 1 2 3 4 5 6 7 8 HS VS GND V GND U GND Y C36 RP3 22Rx4 1 8 2 7 3 6 4 5 C9 0.1uF C93 open R2 3.3K RP4 22Rx4 1 8 2 7 3 6 4 5 C15 0.1uF FB2 1 2 C43 47pF C3 0.1uF R6 10K C543 0.1u C10 1nF C216 0.1uF C8 0.1uF C42 47pF C5 39nF C11 0.1uF R15 22R C6 3.9nF C92 open C13 0.1uF AD9883 LQFP80 U3 AD9883 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 GND GREEN7 GREEN6 GREEN5 GREEN4 GREEN3 GREEN2 GREEN1 GREEN0 GND VDD BLUE7 BLUE6 BLUE5 BLUE4 BLUE3 BLUE2 BLUE1 BLUE0 GND GND VDD VDD GND GND VD VD GND COAST HSYNC VSYNC GND FILT PVD PVD GND MIDSCV CLAMP VD GND GND VD BAIN GND VD VD GND GAIN SOGIN GND VD VD GND RAIN A0 SCA SDA REF BYP VD GND GND VD GND VSOUT SOGOUT HSOUT DATACK GND VDD RED7 RED6 RED5 RED4 RED3 RED2 RED1 RED0 VDD VDD GND RP2 22Rx4 1 8 2 7 3 6 4 5 LM1117MPX-3.3 U1 3 2 1 4 IN OUT GND TAB C572 1u R201 0 C25 4.7pF C474 10uF/16V 1 2 RP1 22Rx4 1 8 2 7 3 6 4 5 R7 120 C475 10uF/35V 1 2 1 2 3 4 LM1117MPX-3.3 SOT223 C37 open FB75 1 2 C35 47pF 5 4 3 2 1 D D C C B B A A ANALOG GND 03 00 S2300 DEINTERLACE C 4 17 Wednesday, January 26, 2005 Title Size Document Number Rev Date: Sheet of PC10 PC8 PC12 PC6 PC1 PC7 PC5 PC4 PC2 PC9 PC13 PC11 PC14 PC0 PC3 PC15 SDRAM_CLK WEN RASN BA1 G/Y0 SDA G/Y1 SCL CSN DQM G/Y3 G/Y2 SDRAM_CLKIN CASN BA0 DATA4 DATA16 ADDR7 ADDR1 DATA10 DU1 DV[0..7] DATA31 DY3 B/U/C4 G/Y4 DAC1.8V DU4 DU5 ADDR8 DATA7 DY4 DU7 DATA23 ADDR3 DATA27 DY1 DV3 DATA0 ADDR4 DU0 DATA30 B/U/C2 DATA14 DATA19 DV0 DV6 DATA3 DU[0..7] ADDR0 DY5 DU3 G/Y7 DATA25 DATA2 DY2 DATA6 DATA13 DV2 DATA[0..31] DV4 ADDR10 B/U/C3 DU6 ADDR5 DATA1 DATA9 DY7 DV1 DATA28 DATA11 B/U/C6 DATA8 DATA5 DATA29 DY[0..7] DATA12 DV7 B/U/C7 B/U/C5 DATA24 DATA17 DATA21 ADDR9 B/U/C1 G/Y6 DV5 B/U/C0 DY6 DATA15 DATA22 ADDR[0..10] G/Y5 DATA20 DU2 ADDR2 DATA26 DY0 ADDR6 DATA18 P2_H P2_5 P2_3 P2_2 P2_4 P2_CLK PC15 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 DI_YCLK MC_SCLK MC_DATA RES_2300# P3.4 Field_ID data_1 P_CLK2 data_6 Hsync data_3 RES_2300# data_4 data_5 data_2 Vsync data_7 data_0 P2_H P2_5 P2_CLK P2_2 P2_4 P2_3 P2_6 P2_ID P2_7 P2_ID P2_7 P2_6 P2_V P2_V MC_SCLK MC_DATA P2_1 P2_1 P2_0 P2_0 SDRAM_CLK 5 DI_VSYNC 10 MC_DATA 3,10,15 BA0 5 2300_VS 3 DQM 5 DI_HSYNC 10 DI_VREF 10 BA1 5 2300_HS 3 WEN 5 RES_2300# 15 SDRAM_CLKIN 5 CASN 5 DI_YCLK 10 P_CLK 3 MC_SCLK 3,10,15 RASN 5 CSN 5 PC[15..0] 10 DI_HREF 10 DY[0..7] 3 DU[0..7] 3 ADDR[0..10] 5 DV[0..7] 3 SDRAM_DATA[0..31] 5 P3.4 3,15 SOG 3 GND GND_ANALOG +3.3VD DAC3.3V GND GND_PLL 3.3V PLL1.8V GND DAC3.3V 3.3V GND DAC1.8V GND GND +1.8V +3.3VD GND DAC3.3V GND GND +1.8VD GND DAC1.8V GND GND GND GND GND 3.3V PLL1.8V +1.8VD +1.8VD PLL1.8V 3.3V GND GND GND GND 3.3V 2.5V GND GND R242 4k7 RP40 22Rx4 1 8 2 7 3 6 4 5 + C505 47UF/16V R231 100 R238 open C502 .1uF/50V RP41 22Rx4 1 8 2 7 3 6 4 5 B probe 1 FB76 1 2 P28A 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 + C489 100uF/16V R232 100 C503 .1uF/50V G probe 1 C486 .1uF/50V 1 2 R233 22 C494 .1uF/50V + C506 47UF/16V C504 .1uF/50V R probe 1 + C485 100UF/16V R235 22 C495 .1uF/50V C508 .1uF/50V R239 22 R236 22 C496 .1uF/50V C500 .1uF/50V C509 .1uF/50V C491 .1uF/50V C497 .1uF/50V C492 .1uF/50V C482 .1uF/50V C510 .1uF/50V C493 .1uF/50V + C479 10UF/16V s2300 U39 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 HSYNC1_PORT1 VSYNC1_PORT1 FIELD ID1_PORT1 IN_CLK1_PORT1 HSYNC2_PORT1 VSYNC2_PORT1 FIELD ID2_PORT1 VDD1(3.3) VSSio IN_CLK2_PORT1 PORT1_A0 PORT1_A1 PORT1_A2 PORT1_A3 PORT1_A4 VDDcore1(1.8) VSScore PORT1_A5 PORT1_A6 PORT1_A7 PORT1_B0 PORT1_B1 PORT1_B2 PORT1_B3 PORT1_B4 PORT1_B5 PORT1_B6 PORT1_B7 PORT1_C0 VDD2(3.3) VSSio PORT1_C1 PORT1_C2 PORT1_C3 PORT1_C4 VDDcore2(1.8) VSScore PORT1_C5 PORT1_C6 PORT1_C7 IN_SEL FILM SYNC_IN DEV_ADDR1 DEV_ADDR0 SCLK SDATA RESET_N VDD3(3.3) VSSio SDRAM DATA0 SDRAM DATA1 SDRM DT2 SDRAM DATA3 SDRAM DATA4 SDRAM DATA5 SDRAM DATA6 SDRAM DATA7 SDRAM DATA8 SDRAM DATA9 SDRAM DATA10 SDRAM DATA11 VDD4(3.3) VSSio SDRAM DATA12 SDRAM DATA13 SDRAM DATA14 SDRAM DATA15 VDDcore3(1.8) VSScore SDRAM DATA16 SDRAM DATA17 SDRAM DATA18 SDRAM DATA19 SDRAM DATA20 SDRAM DATA21 SDRAM DATA22 SDRAM DATA23 SDRAM DATA24 SDRAM DATA25 VDDcore4(1.8) VSScore SDRAM DATA26 SDRAM DATA27 SDRAM DATA28 SDRAM DATA29 SDRAM DATA30 SDRAM DATA31 VDD5(3.3) VSSio TEST IN SDRAM ADDR10 SDRAM ADDR9 SDRAM ADDR8 SDRAM ADDR7 SDRAM ADDR6 VDDcore5(1.8) VSScore SDRAM ADDR5 SDRAM ADDR4 SDRAM ADDR3 SDRAM ADDR2 SDRAM ADDR1 SDRAM ADDR0 WEN OE VID_OUT7 VID_OUT6 VID_OUT5 VID_OUT4 VID_OUT3 VID_OUT2 VID_OUT1 VID_OUT0 VSSio VDD8(3.3) VID_OUT15 VID_OUT14 VID_OUT13 VID_OUT12 VID_OUT11 VID_OUT10 VSScore VDDcore7(1.8) VID_OUT9 VID_OUT8 VID_OUT23 VID_OUT22 VID_OUT21 VID_OUT20 VID_OUT19 VID_OUT18 VSSio VDD7(3.3) VID_OUT17 VID_OUT16 CLKOUT VSScore VDDcore6(1.8) CTLOUT4 CTLOUT3 CTLOUT2 CTLOUT1 CTLOUT0 TEST OUT1 TEST OUT0 TEST3 SDRAM CLKIN VSSio VDD6(3.3) SDRAM CLKOUT DQM CSN BA0 BA1 CASN RASN HSYN_PORT2 VSYN_PORT2 FILDID_PRT2 PORT2_7 PORT2_6 PORT2_5 PORT2_4 PORT2_3 PORT2_2 PORT2_1 VSScore VDDcore8(1.8) PORT2_0 IN_CLK_PORT2 VSSio VDD9(3.3) XTAL OUT XTAL IN TEST2 TEST1 TEST0 DAC_PVDD(3.3) DAC_GR_AVDD(3.3) DAC_GR_AVSS DAC_AVSS DAC_AVDD(3.3) DAC_VREFIN DAC_VREFOUT DAC_RSET DAC_COMP DAC_AVSSR DAC_AVDDR(3.3) DAC_ROUT DAC_AVSSG DAC_AVDDG(3.3) DAC_GOUT DAC_AVSSB DAC_AVDDB(3.3) DAC_BOUT DAC_VSS DAC_VDD(1.8) DAC_PVSS AVSS_PLL_FE AVDD_PLL_FE(1.8) AVDD_PLL_SDI(1.8) AVSS_PLL_SDI AVSS_PLL_BE2 AVDD_PLL_BE2(1.8) AVDD_PLL_BE1(1.8) AVSS_PLL_BE1 PLL_PVSS PLL_PVDD(1.8) C501 .1uF/50V + C507 100uF/16V C517 .1uF/50V C511 .1uF/50V C499 .1uF/50V C518 .1uF/50V C515 .1uF/50V C488 .1uF/50V 1 2 R228 4k7 R241 22 C490 .1uF/50V C484 0.1uF/50V C519 .1uF/50V C514 .1uF/50V + C487 100UF/16V R275 open LM1117MPX-1.8 U40 3 2 1 4 IN OUT GND TAB C520 .1uF/50V C513 .1uF/50V C516 .1uF/50V C512 .1uF/50V R230 187/1% R224 4k7 R225 4k7 R244 100 R226 4k7 + C483 10UF/16V R240 22 22RX4 RP37 1 8 2 7 3 6 4 5 R227 4k7 R245 100 C560 open R237 22 22RX4 RP36 1 8 2 7 3 6 4 5 C498 .1uF/50V 1 2 C480 33pF/5% 1 2 C478 open 1 2 C477 .1uF/50V C481 33pF/5% 1 2 L9 5.6uH + C521 10UF/16V C522 .1uF/50V X1 13.5MHz 1 2 3 RP38 22Rx4 1 8 2 7 3 6 4 5 P24A 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 RP39 22Rx4 1 8 2 7 3 6 4 5 L8 5.6uH R234 47K,5% R243 22 R229 100 5 4 3 2 1 D D C C B B A A DECOUPLING FOR SDRAM 04 00 S2300 SDRAM B 5 17 Wednesday, January 26, 2005 Title Size Document Number Rev Date: Sheet of DATA5 DATA14 DQM ADDR10 DATA17 DATA0 DATA1 ADDR2 DATA19 DATA22 ADDR8 DATA8 DATA26 ADDR7 DATA28 DATA27 DATA31 DATA11 DATA16 DATA12 DATA[0..31] DATA23 ADDR6 SDRAM_CLK DATA13 DATA15 ADDR0 DATA6 DATA21 DATA7 CASN DATA10 BA1 ADDR1 DATA18 ADDR4 DATA4 DATA20 DATA2 DATA24 BA0 ADDR5 DATA25 DATA29 RASN WEN ADDR3 ADDR9 DATA30 SDRAM_CLKIN CSN DATA9 DATA3 DQM 4 CASN 4 SDRAM_DATA[0..31] 4 BA0 4 SDRAM_CLKIN 4 CSN 4 WEN 4 ADDR[0..10] 4 SDRAM_CLK 4 RASN 4 BA1 4 3.3V 3.3V GND GND GND GND GND GND 3.3V R247 NL C532 0.1uF FB94 1 2 R248 4k7/5% C529 0.1uF C527 0.1uF C528 0.1uF RP44 22Rx4 1 8 2 7 3 6 4 5 C534 0.1uF RP42 22Rx4 1 8 2 7 3 6 4 5 C535 0.1uF C524 .1uF/50V C538 0.1uF C523 .1uF/50V C537 0.1uF C525 .1uF/50V C536 0.1uF KM432S2030C 86 PIN TSOP U35 KM432S2030C 2 4 5 7 8 10 11 13 74 76 77 79 80 82 83 85 25 26 27 60 61 62 63 64 65 66 24 1 86 72 58 6 32 12 38 15 29 3 9 35 41 49 46 30 57 69 70 73 22 23 19 18 20 17 68 67 14 21 31 33 34 36 37 39 40 42 45 47 48 50 51 53 54 56 16 71 28 59 55 75 81 43 52 78 84 44 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 VDD VSS VSS VSS VSSQ VSSQ VSSQ VSSQ VDD VDD VDDQ VDDQ VDDQ VDDQ VDDQ VSSQ NC NC NC NC NC BA0 BA1 RAS CAS CS WE CLK CKE NC NC DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQM0 DQM1 DQM2 DQM3 VDDQ VDDQ VDDQ VDD VSSQ VSSQ VSSQ VSS R246 100/5% RP43 22Rx4 1 8 2 7 3 6 4 5 +C526 2.2uF/25V C531 0.1uF FB93 1 2 C530 0.1uF C533 0.1uF 5 4 3 2 1 D D C C B B A A 1 TO JAGASM ADC 3 2 CUT IN GND PLANE AND JOIN NEAR JAG 2 1 BAV99 FOOTPRINT 3 CUT IN GND PLANE AND JOIN NEAR ANALOG POWER SUPPLY EDID DATA 00 VGA CONNECTOR Custom 6 17 Wednesday, January 26, 2005 Title Size Document Number Rev Date: Sheet of ARED1N DDDA DDCK RED1 BLUE1 BLUE1 GREEN1 RED1 GREEN1 PVSI1 PHSI1 VGA_+5V VGA_+5V +5V BLUE-GND GREEN-GND RED-GND AGREEN1N RED1 GREEN1 BLUE1 ARED1N 7 AGREEN1N 7 VGA_HSYNC 10 ARED1P 7 ABLUE1P 7 ABLUE1N 7 AGREEN1P 7 VGA_VSYNC 10 GND A+5V GND GND GND GND GND GND +5V GND GND GND GND GND GND A+5V A+5V A+5V GND 3.3V GND +5V A+5V GND R36 75 1% R48 1K C77 1u R211 0 C558 0.01u D1 1 2 3 D4 BAV99 1 2 3 R210 0 VGA P11 ASTRON HDB600-15 1 2 3 13 14 12 15 6 7 8 5 11 4 10 16 17 9 RED GREEN BLUE HSYNC VSYNC DDDA(ID1) DDCK(ID3) RGND GGND BGND GND ID0 ID2 GND MH1 MH2 VCC R209 0 FB56 1 2 C559 1u FB57 1 2 D10 BAV99 1 2 3 C78 2.2pf R286 100R D11 BAV99 1 2 3 R33 75 1% D12 BAV99 1 2 3 C80 2.2pf C573 1u FB12 1 2 R34 0R 1% R52 10K C79 1u R44 100R R28 75 1% R284 open R285 open R32 75 R50 10K DDC U8 ST24FW21 4 5 6 3 8 7 1 2 GND SDA SCL WC VCC VCLK NC1 NC2 SOT23 D7 BAT54C/BAV70 2 3 1 R30 0R C87 0.1uF R45 100R U41 7414 14 7 1 3 5 9 11 13 2 4 6 8 10 12 FB55 1 2 D21 DIODE C76 2.2pf R49 1K R46 100R R37 75 1% C75 1u R38 0R D2 1 2 3 FB13 1 2 R47 100R D3 1 2 3 C85 100pf R29 75 1% C86 100pf R51 10K 5 4 3 2 1 D D C C B B A A 2.5V ANALOG POWER CAPTURE PLL GND QUIET ANALOG GND UNDER THESE LINES GND PLANE MUST BE CUT FROM VGA AS SHOWN ON VGA SHEET. DIGITAL PLL GND 00 JAGUAR ANALOG INTERFACE Custom 7 17 Wednesday, January 26, 2005 Title Size Document Number Rev Date: Sheet of ABLUE1N 6 ABLUE1P 6 AGREEN1N 6 ARED1P 6 ARED1N 6 AGREEN1P 6 GND 2.5V GND GND GND GND 3.3V JA2.5V1 3.3V GND GND 2.5V JA2.5V2 JA2.5V2 JA2.5V1 JA2.5V1 GND GND JA2.5V1 JA2.5V2 JA2.5V1 GND +5V GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND R57 10 C110 1u C115 0.1uF C116 10uF/16V C91 10uF/16V C96 1nF C112 1u C90 10uF/16V FB19 1 2 C101 0.1uF FB17 1 2 C111 0.1uF C121 1u FB21 1 2 C117 1nF FB15 1 2 C113 0.1uF C118 0.1uF R212 47 C102 1nF FB20 1 2 C100 0.1uF C99 0.1uF LM1117MPX-2.5 U9 3 2 1 4 IN OUT GND TAB R217 open FB14 1 2 C107 0.1uF R53 22R C94 10pF C114 10uF/16V JAGUAR - ANALOG U11D JAGUAR A6 A7 A10 A11 A14 A15 A18 A19 A12 A13 A16 A17 A20 A21 C14 C15 C16 C17 C18 C19 C12 C13 A8 A9 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 C7 C20 C8 C9 C10 C11 C21 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 B22 C22 A22 D22 XIN XOUT R2N R2P G2N G2P B2N B2P R1N R1P G1N G1P B1N B1P RREFL RREFH GREFL GREFH BREFL BREFH IREFL IREFH I1 I2 XVSS CVSS2 CVSS1 DVSS IVSS2 IVSS1 RVSS2 RVSS1 GVSS2 GVSS1 BVSS2 BVSS1 SVSS PVSS1 GPVSS AVSS2 AVSS1 AVDD3 AVDD4 AVDD1 AVDD2 GPVDD XVDD CVDD2 CVDD1 DVDD IVDD2 IVDD1 RVDD2 RVDD1 GVDD2 GVDD1 BVDD2 BVDD1 SVDD PVDD1 VDDP1 VDDP2 VSSP1 VSSP2 C105 1nF C120 0.1uF C104 10uF/16V R54 10R C103 1nF FB22 1 2 C106 1uF/25V R55 10R C119 0.1uF R56 47 C98 0.1uF FB16 1 2 C108 0.1uF C109 1u U10 14.318MHz OSC 3 4 2 1 O VD G N C89 1nF C454 10pF 5 4 3 2 1 D D C C B B A A 00 JAG SARAM INTERFACE Custom 8 17 Wednesday, January 26, 2005 Title Size Document Number Rev Date: Sheet of SD35 SA9 SD34 SD9 TSWE# SA6 SCAS# SD13 SA1 SA7 SD42 SD43 SA4 SD10 SD56 TSCAS# SD5 SCS# TSA5 SD2 SD48 SD49 SD32 TSA8 SD6 SD22 SD7 SD51 SA4 SD40 SD57 SCKE# SA2 SCKE SCAS# SA5 SA5 SD8 SA10 SD1 SD27 SA0 SD60 SD25 SD36 SD54 SD0 SA10 TSA[10..0] SD17 SA8 SWE# SD28 SD29 SA6 SD44 SD16 SA7 TSA10 TSA0 SD24 SD30 TSDQM SD50 SRAS# SD[63..0] SWE# SD23 SDQM SD45 SD46 TSA3 SD59 SA0 SCLK SD63 SD41 SA3 SRAS# SA2 SD11 SD26 SD31 SD12 SDQM TSA7 SD53 SD3 SD21 SD14 SD61 TSA9 SD52 SD37 TSRAS# TSA4 SD38 SA8 SD47 SD20 SD19 TSA2 SD55 SA3 TSA6 SA1 SD4 SBA# SD58 SD15 SD18 SCS# SBA# TSBA0 SD39 TSA1 SD33 SA9 SD62 TSCLK TSWE# 9 TSCKE 9 TSDQM 9 SD[63..0] 9 TSCLK 9 TSBA0 9 TSRAS# 9 TSBA1 9 TSA[10..0] 9 TSCAS# 9 TSCS# 9 X1 15 GND GND 3.3V GND GND 2.5V C131 0.1uF 22RX4 RP14 1 8 2 7 3 6 4 5 C127 0.1uF C126 0.1uF R59 0R 22RX4 RP11 1 8 2 7 3 6 4 5 22RX4 RP13 1 8 2 7 3 6 4 5 R60 22R OR6 open C122 0.1uF FB23 1 2 R190 100 C129 0.1uF C128 0.1uF R58 0R 22RX4 RP12 1 8 2 7 3 6 4 5 C124 0.1uF C123 0.1uF C125 0.1uF 22RX4 RP15 1 8 2 7 3 6 4 5 C130 0.1uF JAGUAR - SDRAM U11B JAGUAR AD22 AE22 AC23 AD23 AE23 AC24 AD24 AE24 AF24 AC25 AD25 AE25 AF25 AD26 AE26 AB24 AB25 AB26 AA23 AA24 AA25 AA26 Y23 Y24 Y25 W24 W25 W26 L23 L24 L25 K24 K25 K26 J23 J24 J25 H23 H24 H25 H26 G24 G25 G26 F23 F24 F25 E23 E24 E25 E26 D24 D25 D26 C23 C24 C25 C26 B23 B24 B25 B26 A24 A25 V23 V24 V25 V26 U23 U24 U25 P25 P26 N24 N25 T24 T25 T26 R23 R24 R25 P23 P24 M23 M24 M25 M26 A26 J26 N26 U26 Y26 AF26 D23 K23 T23 AB23 A23 F26 L26 R26 AC26 AF23 G23 N23 W23 D21 SDD00 SDD01 SDD02 SDD03 SDD04 SDD05 SDD06 SDD07 SDD08 SDD09 SDD10 SDD11 SDD12 SDD13 SDD14 SDD15 SDD16 SDD17 SDD18 SDD19 SDD20 SDD21 SDD22 SDD23 SDD24 SDD25 SDD26 SDD27 SDD28 SDD29 SDD30 SDD31 SDD32 SDD33 SDD34 SDD35 SDD36 SDD37 SDD38 SDD39 SDD40 SDD41 SDD42 SDD43 SDD44 SDD45 SDD46 SDD47 SDD48 SDD49 SDD50 SDD51 SDD52 SDD53 SDD54 SDD55 SDD56 SDD57 SDD58 SDD59 SDD60 SDD61 SDD62 SDD63 SDA0 SDA1 SDA2 SDA3 SDA4 SDA5 SDA6 SDA7 SDA8 SDA9 SDA10 MEMCLK SDCKFB SDCAS# SDCKP SDCKE SDWE# SDCKN SDRAS# DQM BANK DQS SDCS0 VDD VDD VDD VDD VDD VDD VDDC VDDC VDDC VDDC VSS VSS VSS VSS VSS VSS VSSC VSSC VSSC VDDC 5 4 3 2 1 D D C C B B A A DECOUPLING FOR SDRAMS 00 SDRAM BASED FRAM BUFFER Custom 9 17 Wednesday, January 26, 2005 Title Size Document Number Rev Date: Sheet of TSA4 SD58 SD49 SD53 SD52 SD42 TSA2 SD31 TSA1 SD35 SD13 TSA8 TSA3 SD16 TSA7 SD12 SD5 SD9 SD37 SD40 SD59 SD25 SD43 TSA6 SD57 SD8 SD60 SD7 SD3 SD28 TSA6 SD24 SD61 SD48 TSA1 SD21 SD1 SD32 TSA5 SD18 SD6 SD38 TSA9 SD0 TSA10 SD14 TSA3 SD20 SD50 TSA4 SD29 TSA0 SD62 SD54 SD63 SD17 TSA9 SD44 TSA8 SD11 SD23 SD[63..0] SD46 SD36 TSA[10..0] SD33 SD41 SD15 SD30 SD34 SD2 SD26 TSA10 SD56 TSA0 SD10 TSA5 SD39 TSA2 SD55 SD51 SD45 SD27 SD19 SD4 SD22 TSA7 SD47 SD[63..0] 8 TSCS# 8 TSCAS# 8 TSBA1 8 TSRAS# 8 TSDQM 8 TSWE# 8 TSBA0 8 TSA[10..0] 8 TSCLK 8 TSCKE 8 GND GND 3.3V GND 3.3V 3.3V 3.3V GND GND GND GND 3.3V 3.3V 3.3V C143 0.1uF C140 0.1uF C141 0.1uF K4S643232C U12 K4S643232C-TC/L70 25 26 27 60 61 62 63 64 65 66 24 2 4 5 7 8 10 11 13 74 76 77 79 80 82 83 85 68 67 20 19 18 17 16 71 23 14 21 3 9 35 41 1 15 6 12 32 38 44 58 30 57 69 70 73 31 33 34 36 37 39 40 42 45 47 48 53 56 22 28 59 29 46 54 51 49 50 52 55 72 86 43 75 81 78 84 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CLK CKE CS RAS CAS WE DQM0 DQM1 BA1 NC1 NC2 VCCQ VCCQ VCCQ VCCQ VCC VCC VSSQ VSSQ VSSQ VSSQ VSS VSS NC3 NC4 NC5 NC6 NC7 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ29 DQ31 BA0 DQM2 DQM3 VCC VSSQ DQ30 DQ28 VCCQ DQ27 VSSQ VCCQ VSS VSS VCC VCCQ VCCQ VSSQ VSSQ C142 0.1uF K4S643232C U13 K4S643232C-TC/L70 25 26 27 60 61 62 63 64 65 66 24 2 4 5 7 8 10 11 13 74 76 77 79 80 82 83 85 68 67 20 19 18 17 16 71 23 14 21 3 9 35 41 1 15 6 12 32 38 44 58 30 57 69 70 73 31 33 34 36 37 39 40 42 45 47 48 53 56 22 28 59 29 46 54 51 49 50 52 55 72 86 43 75 81 78 84 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CLK CKE CS RAS CAS WE DQM0 DQM1 BA1 NC1 NC2 VCCQ VCCQ VCCQ VCCQ VCC VCC VSSQ VSSQ VSSQ VSSQ VSS VSS NC3 NC4 NC5 NC6 NC7 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ29 DQ31 BA0 DQM2 DQM3 VCC VSSQ DQ30 DQ28 VCCQ DQ27 VSSQ VCCQ VSS VSS VCC VCCQ VCCQ VSSQ VSSQ FB80 1 2 FB81 1 2 FB82 1 2 FB83 1 2 C136 0.1uF C135 0.1uF C134 0.1uF C144 22uF/16V C133 0.1uF C132 0.1uF C149 0.1uF C145 22uF/16V C148 0.1uF C137 0.1uF C147 0.1uF C139 0.1uF C146 0.1uF C138 0.1uF C157 0.1uF C155 0.1uF R61 10k C156 0.1uF C152 0.1uF C153 0.1uF C154 0.1uF C150 0.1uF C151 0.1uF 5 4 3 2 1 D D C C B B A A SAME COPPER ISLAND ON L4 GPIO4:internal PLL clock output 00 JAG DIGITAL INTERFACE Custom 10 17 Wednesday, January 26, 2005 Title Size Document Number Rev Date: Sheet of VGA_VSYNC PC8 PC10 MCAD0 MCAD5 JWR# PC4 DI_HSYNC DVI_VSYNC PC7 PC14 DI_YCLK PC5 PC11 PC1 PC6 MCAD4 PC2 PC9 PC13 MCAD1 INTR_ASM# PC12 MCAD3 MCAD6 MCA8 MCAD[7..0] MCAD7 DI_VSYNC RESET# DI_VREF DI_HREF MCALE JRD# PC0 PC15 MCAD2 PC3 MCA9 PAR7 PAR2 PAR5 PAG1 PAG0 PAR6 PAR1 PAR0 PAG7 PAG4 PAG6 PAR3 PAG3 PAG5 PAG2 PAR4 PAB0 PAB2 PAB4 PAB6 PAB1 PAB7 PAB5 PAB3 DVICK DVI_HSYNC VGA_HSYNC DDE MCA9 15 VGA_VSYNC 6 MCALE 15 INTR_ASM# 15 JWR# 15 RESET# 15 DI_YCLK 4 MC_DATA 3,4,15 VGA_HSYNC 6 PC[15..0] 4 DI_VREF 4 MC_SCLK 3,4,15 DI_HREF 4 MCA8 15 JRD# 15 MCAD[7..0] 15 PD_DVI 14 DI_VSYNC 4 DI_HSYNC 4 PAG[7..0] 14 PAB[7..0] 14 PAR[7..0] 14 DVIDE 14 DVI_HSYNC 14 DVICK 14 DVI_VSYNC 14 CTRL_SOURCE 3 DVI_RESET# 14 3.3V 2.5V GND GND 3.3V GND GND GND GND GND GND GND 3.3V R72 220 R218 4k7 PORT A PORT B PORT C CPU JAGUAR - DIGITAL U11A JAGUAR P1 P2 N2 N3 M1 M2 M3 M4 L1 L2 L3 L4 K2 K3 K4 J1 J2 J3 J4 H1 H2 H3 G1 G2 G4 F1 F2 G3 AA2 AA3 Y1 Y2 Y3 W1 W2 W3 W4 V1 V2 V3 V4 U1 U2 U3 U4 T1 T2 T3 T4 R1 R2 R3 P4 C6 P3 AF1 AF2 AF3 AF4 AE1 AE2 AE3 AE4 AD1 AD2 AD3 AD4 AC1 AC2 AC3 AC4 AA4 AB2 AB3 AB1 B6 B5 C5 D5 A4 B4 A3 B3 C3 A2 D3 E3 E4 E1 D2 E2 A1 C2 B2 F4 F3 AD5 AE5 D1 A5 H4 K1 R4 AB4 AA1 C1 N1 D4 N4 Y4 AC5 D6 C4 PA00 PA01 PA02 PA03 PA04 PA05 PA06 PA07 PA08 PA09 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PCLKA DEIN HSYNC0 DVSYNC PB00 PB01 PB02 PB03 PB04 PB05 PB06 PB07 PB08 PB09 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PCLKB HSYNC2 PBVSYNC PC00 PC01 PC02 PC03 PC04 PC05 PC06 PC07 PC08 PC09 PC10 PC11 PC12 PC13 PC14 PC15 PCLKC PCHREF PCHSYNC PCVSYNC MCAD0 MCAD1 MCAD2 MCAD3 MCAD4 MCAD5 MCAD6 MCAD7 MCA8 MCA9 MCALE MCRD# MCWR# SYSRST# INTR# PWM1/GPIO0 CLAMPOUT HSYNCOUT GPIO4 SDA SCL PCVREF/GPIO2 PCFIELD/GPIO3 TEST VDD VDDC VDD VDDC VDDC VDD VSS VSS VSSC VSSC VSSC VSS HSYNC1 MCCS# R64 1k R65 1k R70 open R73 4.7k R75 4.7k C160 0.1uF R63 10K FB25 1 2 C159 0.1uF C163 0.1uF C162 0.1uF C161 0.1uF C158 0.1uF R62 10K 5 4 3 2 1 D D C C B B A A 00 JAG PANEL INTERFACE Custom 11 17 Wednesday, January 26, 2005 Title Size Document Number Rev Date: Sheet of P4 P16 P21 P8 P12 P1 P7 PENVDD P41 P36 P27 P22 P14 P3 P24 P31 P32 P26 P28 P30 P42 P9 P34 P10 P20 PNLCLK PENBKL P18 P11 P25 P38 P44 P23 P6 P19 P46 P35 P2 P0 P47 P37 P45 P33 P39 P13 P40 P5 P17 P29 P43 P15 PVSYNC PHSYNC PDE PENBKL 12 PENVDD 12,13 P[23..0] 12 P[47..24] 12 PSHFCLK 12,13 PHSYNC 13 PDE 12,13 PVSYNC 12,13 PWM1 12 GND GND 2.5V GND GND 3.3V GND C168 0.1uF C165 0.1uF C169 0.1uF R11_1 open 100RX4 RP28 1 8 2 7 3 6 4 5 C166 0.1uF R87 22R JAGUAR - PANEL U11C JAGUAR AF5 AC6 AD6 AE6 AF6 AC7 AD7 AE7 AF7 AD8 AE8 AC9 AD9 AE9 AF9 AC10 AD10 AE10 AD11 AE11 AF11 AC12 AD12 AE12 AD13 AE13 AD14 AE14 AF14 AC15 AD15 AE15 AF15 AC16 AD16 AE16 AD17 AE17 AF17 AC18 AD18 AE18 AF18 AC19 AD19 AE19 AD20 AE20 AC21 AE21 AF20 AF12 AD21 AF22 AC13 AF10 AF16 AF21 AC8 AC14 AC20 AF8 AF13 AF19 AC11 AC17 AC22 B1 P11 P12 P13 P14 P15 P16 L11 L12 L13 L14 L15 L16 M11 M12 M13 M14 M15 M16 N11 N12 N13 N14 N15 N16 T11 T12 T13 T14 T15 T16 R11 R12 R13 R14 R15 R16 PD00 PD01 PD02 PD03 PD04 PD05 PD06 PD07 PD08 PD09 PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17 PD18 PD19 PD20 PD21 PD22 PD23 PD24 PD25 PD26 PD27 PD28 PD29 PD30 PD31 PD32 PD33 PD34 PD35 PD36 PD37 PD38 PD39 PD40 PD41 PD42 PD43 PD44 PD45 PD46 PD47 PVSYNC PHSYNC PDE PNLCLK ENVDD ENBKL PSHFCLK VDD VDD VDD VDDC VDDC VDDC VSS VSS VSS VSSC VSSC VSSC PWM1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS FB26 1 2 C164 0.1uF C167 0.1uF 5 4 3 2 1 D D C C B B A A Use Pin Compatible Si9934DY for 3.3V Panels C BACKLIGHT E 3 B DTC144EKA FOOTPRINT 2 1 OUTPUT IS 24BIT : P0-P7(B0-B7) P8-P15(G0-G7) P16-P23(R0-R7) OUTPUT IS 48BIT : P0-P7(FB0-FB7) P8-P15(SB0-SB7) P16-P23(FG0-FG7) P24-P31(SG0-SG7) P32-P39(FRO-FR7) P40-P47(SRO-SR7) 排板时公共端重叠 00 PANEL INTERFACE Custom 12 17 Wednesday, January 26, 2005 Title Size Document Number Rev Date: Sheet of P40 P28 P12 P3 P44 P11 P1 P20 P15 P9 P0 P13 P16 P34 P14 P43 P25 P10 P21 P31 P32 P27 P2 P5 P19 P41 P45 P37 P22 P39 P30 P17 P33 P4 P42 P46 P8 P38 P6 P24 P29 P47 P7 P35 P36 P23 P18 P26 PENVDD PENVDD FP45 FP27 FP31 FP44 FP39 FP28 FP43 FP42 FP35 FP34 FP[47..24] FP33 FP29 FP38 FP46 FP26 FP36 FP24 FP30 FP25 FP41 FP37 FP40 FP32 FP47 VDDSW ON/OFF FP6 FP2 FP7 FP15 FP8 FP18 FP10 FP20 FP14 FP23 FP0 FP1 FP4 FP22 FP19 FP11 FP17 FP12 FP9 FP13 FP16 FP[23..0] FP3 FSHFCLK FHSYNC FP5 FP21 FDE PNLPWR PENBKL 11 PSHFCLK 11,13 PENVDD 11,13 PWM1 11 PHSYNC 11,13 P[23..0] 11 FP[23..0] 13 P[47..24] 11 FP[47..24] 13 PDE 11,13 FHSYNC VDDSAFE 13 FDE 11,13 FSHFCLK 11,13 PVSYNC 11,13 FVSYNC 11,13 +5V GND GND GND GND GND GND GND +5V GND 3.3V GND INV-12V INV-12V GND 3.3V +5V pannle_12V +5V GND GND GND R69 open C173 1uF Q5 DTC144EKA open 1 2 3 100RX4 RP19 1 8 2 7 3 6 4 5 C171 0.1uF OR8 0 P7 JST-S7B-PH-K 1 2 3 4 5 6 7 +15V GND BRT NC ON/OFF GND +15V R82 5.1K open R80 47k 100RX4 RP20 1 8 2 7 3 6 4 5 100RX4 RP17 1 8 2 7 3 6 4 5 Q4 DTC144EKA 1 2 3 R12_1 0 or open R12_2 0 or open R12_3 0 or open 100RX4 RP18 1 8 2 7 3 6 4 5 C170 10uF/35V R78 6.8k 100RX4 RP23 1 8 2 7 3 6 4 5 100RX4 RP21 1 8 2 7 3 6 4 5 100RX4 RP26 1 8 2 7 3 6 4 5 C554 0.1uF F2 FUSE-3A 速熔 1 2 C555 0.1uF 100RX4 RP25 1 8 2 7 3 6 4 5 C556 0.1uF C557 0.1uF C172 0.1uF 100RX4 RP16 1 8 2 7 3 6 4 5 R270 6.8k 100RX4 RP22 1 8 2 7 3 6 4 5 R268 open OR9 open R79 4.7K C422 0.1uF R269 open FB67 1 2 100RX4 RP27 1 8 2 7 3 6 4 5 P-MOS U14A Si9953DY 2 8 7 1 3 4 5 6 G D D S S2 G2 D2 D2 R77 0 FB68 1 2 Q3 DTC144EKA 1 2 3 FB69 1 2 Q7 open 3 1 2 C423 0.1uF 100RX4 RP24 1 8 2 7 3 6 4 5 5 4 3 2 1 D D C C B B A A open for 15~23 inch pannel,0 for 30inch pannel 布板时此处电阻尽量靠近 CN1 LVDS LVDS LVDS PIN11~PIN30 LVDS PI 为单 接口与双 接口共用插排，单 接口用 ；双 接口用 N1~PIN30。 CN14 15'20' 删除， 23' 0 for 15~23 inch pannel,open for 30inch pannel 00 LVDS PANEL C 13 17 Wednesday, January 26, 2005 Title Size Document Number Rev Date: Sheet of PENAB1 RxE1- RxE3- RxE3+ RxE0- RxEC+ RxEC- PLLVCC PVS1 RxE2- LVDSVCC PHS1 RxE2+ RxE1+ RxE0+ FP15 FP8 FP13 FP12 FP6 FP7 FP2 FP11 FP21 FP19 FP5 FP4 FP1 FP20 FP14 FP16 FP23 FP22 FP3 FP0 FP18 FP9 FP17 FP10 RxE3+ RxE3- RxEC+ RxEC- RxO3- RxO1+ RxE1- RxO0+ RxO1- RxOC+ RxO2+ RxE2- RxO2- RxO3+ RxE1+ RxO0- RxOC- RxE2+ RxE0+ RxE0- FP[47..24] LVDSVCC RxO2- RxO1- RxOC- RxOC+ RxO0- RxO3+ RxO1+ RxO3- PLLVCC RxO0+ RxO2+ PCLK FP31 FP34 FP44 FP42 FP39 FP41 FP37 FP27 FP33 FP36 FP35 FP30 FP46 FP24 FP38 FP25 FP28 FP29 FP40 FP26 FP47 FP43 FP32 PENAB PHS PVS FP45 PVSYNC 11,12 PDE 11,12 PSHFCLK 11,12 PENVDD 11,12 PENVDD 11,12 FP[23..0] 12 PHSYNC 11 VDDSAFE 12 FP[47..24] 12 PHSYNC 11,12 PVSYNC 11,12 PDE 11,12 PSHFCLK 11,12 PENVDD 11,12 PENVDD 11,12 VDDSAFE 12 GND PLLVCC LVDSVCC GND GND 3.3V 3.3V GND GND GND GND 3.3V 3.3V GND PLLVCC LVDSVCC GND 3.3V 3.3V GND GND GND GND GND GND GND GND GND 3.3V 3.3V GND GND C578 1u C13_6 0.1uF C465 22uF/16v C177 0.01uF FB61 BEAD POWER C466 220PF C189 22uF C184 22uF R106 47 C464 0.1uF C183 0.1uF C191 0.01UF C185 220PF C190 220PF R85 0 FB29 BEAD POWER R96 47 C178 0.01uF R97 open R84 0 C576 1u R13_5 0 or open R13_6 0 or open R13_7 0 or open R13_8 0 or open C470 10uF/35V R83 47 C577 1u C13_7 0.01uF C575 1u C13_8 0.01uF R185 0 or open R187 47 R84_1 0 R189 0 or open C13_5 22UF/16v R188 0 or open CN1 CON30 1 2 3 4 5 6 7 10 13 15 17 19 21 23 25 26 27 28 29 30 22 24 18 16 20 14 12 9 8 11 RXE3+ RXE3- RXEC+ RXEC- RXE2+ RXE2- RXE1+ RXE0- RXO3+ GND RXOC- RXO2+ GND RXO1- RXO0+ RXO0- VDD VDD VDD VDD RXO1+ GND GND RXOC+ RXO2- RXO3- GND RXE0+ RXE1- GND R183 47 R186 0 or open R184 open C446 open C176 0.1uF U13_1 SN75LVDS83 48 52 54 46 55 56 3 50 2 4 6 7 12 42 14 8 10 15 19 20 38 22 23 24 16 18 27 28 30 25 31 17 39 47 45 41 37 40 1 9 26 5 13 21 53 49 43 36 44 35 33 34 32 51 11 11 11 11 29 Y0M D1 D2 Y1M D3 D4 D6 D27 D5 D7 D8 D9 D13 Y2M D14 D10 D11 D15 D18 D19 Y3M D20 D21 D22 D16 D17 D24 D25 D26 D23 CLKIN CLKSEL CLKOUTP Y0P Y1P Y2P Y3P CLKOUTM VCC VCC VCC GND GND GND GND LVDSGND LVDSGND LVDSGND LVDSVCC PLLGND PLLGND PLLVCC /SHTDN D0 D12 D12 D12 D12 GND C223 10pF R85_1 0 R182 47 FB60 BEAD POWER C174 22UF C463 22uF/16v U15 SN75LVDS83 48 52 54 46 55 56 3 50 2 4 6 7 12 42 14 8 10 15 19 20 38 22 23 24 16 18 27 28 30 25 31 17 39 47 45 41 37 40 1 9 26 5 13 21 53 49 43 36 44 35 33 34 32 51 11 11 11 11 29 Y0M D1 D2 Y1M D3 D4 D6 D27 D5 D7 D8 D9 D13 Y2M D14 D10 D11 D15 D18 D19 Y3M D20 D21 D22 D16 D17 D24 D25 D26 D23 CLKIN CLKSEL CLKOUTP Y0P Y1P Y2P Y3P CLKOUTM VCC VCC VCC GND GND GND GND LVDSGND LVDSGND LVDSGND LVDSVCC PLLGND PLLGND PLLVCC /SHTDN D0 D12 D12 D12 D12 GND C462 0.01UF FB28 BEAD POWER C196 open C461 220PF 5 4 3 2 1 D D C C B B A A DVI CONNECTOR PLACE TERMINATION RESISTANCE AT OUTPUTS BASED ON ROUTE LENGTH 第一版用插件， HDCP 以后要注意 的要求 00 DVI INTERFACE B 14 17 Wednesday, January 26, 2005 Title Size Document Number Rev Date: Sheet of RX2- RX0+ RX2+ RX0- RX1- RX1+ RXC+ PAR7 PAR6 PAR5 PAR4 PAR0 PAR1 PAR2 PAR3 PAB6 PAG3 PAG6 PAB0 PAG1 PAG5 PAG2 PAG0 PAB2 PAB7 PAG7 PAB3 PAB5 PAB4 PAG4 PAB1 RX0+ RX2+ DVI_VSYNC DVIDE RX0- RX1- RX1+ RX2- DVI_HSYNC RXC+ DVICK DVI_SDA RXC- RXC- DVI_SCL DVI_SDA DVI_SCL DVI_HSYNC 10 DVI_VSYNC 10 DVIDE 10 PAG[7..0] 10 PAR[7..0] 10 PAB[7..0] 10 DVICK 10 DVI_RESET# 10 PD_DVI 10 3.3V GND DAVCC1 3.3V GND DAVCC1 GND GND 3.3V 3.3V GND GND +5V GND 3.3V 3.3V GND GND 3.3V GND 3.3V 3.3V GND GND 3.3V GND GND GND GND GND GND +5V +5V 3.3V C440 10nF U29 X24C04S8 1 2 3 4 5 6 7 8 A0 A1 A2 GND SDA SCL TEST VCC C432 open(EP169) 0.1u(sil169) P10 1 2 3 4 5 14 13 12 9 10 15 17 18 20 21 7 6 22 19 24 16 11 23 28 8 25 26 27 RX2- RX2+ SHLD2/4 RX4- RX4+ +5V RX3+ RX3- RX1- RX1+ GND RX0- RX0+ RX5- RX5+ DDC_DAT DDC_CLK SHLDC SHLD0/5 RXC- HPD SHLD1/3 RXC+ AHSYNC AVSYNC ARED AGREEN ABLUE OR13 4k7 C436 10nF C549 open C425 100pF R193 4k7(EP169) 0(sil169) R194 4k7(EP169) open(sil169) U42 X24C04S8(open) 1 2 3 4 5 6 7 8 A0 A1 A2 GND SDA SCL TEST VCC C427 100pF R167 4k7 C548 open C438 10nF R169 open C437 10nF R178 open C433 0.1uF R180 open C439 10nF R191 open C430 100pF R192 open C435 0.1uF TMDS RECEIVER U28 Sil161 10 11 12 13 14 15 16 17 20 21 22 23 24 25 26 27 30 31 32 33 34 35 36 37 49 50 51 52 53 54 55 56 60 61 62 63 64 65 66 69 70 71 72 73 59 74 75 77 96 80 81 85 86 90 91 93 94 82 84 88 95 79 83 87 89 92 97 98 6 38 67 68 39 5 18 29 43 57 78 76 58 45 28 19 44 46 47 48 40 41 42 9 8 1 2 3 4 7 99 100 QE0 QE1 QE2 QE3 QE4 QE5 QE6 QE7 QE8 QE9 QE10 QE11 QE12 QE13 QE14 QE15 QE16 QE17 QE18 QE19 QE20 QE21 QE22 QE23 QO0 QO1 QO2 QO3 QO4 QO5 QO6 QO7 QO9 QO10 QO11 QO12 QO13 QO14 QO15 QO16 QO17 QO18 QO19 QO20 QO8 QO21 QO22 QO23 EXT_RES RX2+ RX2- RX1+ RX1- RX0+ RX0- RXC+ RXC- AVCC AVCC AVCC AVCC AGND AGND AGND AGND AGND PVCC PGND CVCC CVCC/SCL2 CVCC GND GND/SDA2 GND OVCC OVCC OVCC OVCC OVCC OGND OGND OGND OGND OGND ODCK DE VSYNC HSYNC (CTL1)HS_DJTR (CTL2)OCK_INV CTL3 PDO SCDT (HS_DJTR)RESET# PD SDA(ST) PIXS STAG_OUT RESERVED SCL(OCK_INV) C426 100pF R181 4k7 R168 4.7k C431 0.1uF RP30 22Rx4 1 8 2 7 3 6 4 5 RP31 22RX4 1 8 2 7 3 6 4 5 C428 100pF RP32 22RX4 1 8 2 7 3 6 4 5 RP33 22RX4 1 8 2 7 3 6 4 5 R197 open(EP169) 0(Sil169/161) RP34 22RX4 1 8 2 7 3 6 4 5 D19 BAV99 1 2 3 RP35 22RX4 1 8 2 7 3 6 4 5 D18 BAV99 1 2 3 R173 open SOT23 D6 BAT54C/BAV70 1 2 3 R170 open R171 4.7K R174 390 RP29 22Rx4 1 8 2 7 3 6 4 5 R195 open R172 4.7K R196 open R166 open U49 NDC7002N 1 2 3 4 5 6 G1 S2 G2 D2 S1 D1 FB50 1 2 R175 100 R176 100 FB51 1 2 R289 1k FB52 1 2 C404 0.1uF C434 10uF/16V 1 2 R177 4.7K C429 10uF/16V 1 2 R165 22R C424 10uF/16V 1 2 R179 4.7K 5 4 3 2 1 D D C C B B A A BIOS CONFIGURATION DATA W27C020/SST29E020 80C32PLCC 29EE010-DIP32 RESET DEBUG PORT 00 MICROCONTROLLER 80C251 A3 15 17 Wednesday, January 26, 2005 Title Size Document Number Rev Date: Sheet of INTR_ASM# MCALE MC_DATA 2596_ON RESET PSEN# FLASHWE# EA# RXD TXD MC_SCLK FLASHCE# 2000-2FFF 3000-3FFF MCA16 MCA16 EA# MCA17 MCA17 MCA16 MCA17 MCA15 MCWR# FLASHWE# MCA14 MCA16 FLASHWE# REMOT MCA16 MCA17 MCA17 MCRD# SDA_analog REMOT INTR_analog MCA14 MCA12 MCA13 MCA15 MCA14 PSEN# MCA15 MCWR# JAGUAR# MCRD# JAGUAR# FLASHCE# MCWR# FLASHCE# MCA11 MCA10 MCA12 MCAD6 MCA10 MCAD0 MCA12 MCA8 MCA9 MCAD1 MCA14 MCAD7 MCAD0 MCA4 MCA[15..0] MCAD6 MCAD7 MCAD5 MCAD1 MCA8 MCA5 MCAD3 MCA6 MCA1 MCA1 MCA1 MCA12 MCA8 MCA13 MCA14 MCAD4 MCAD5 MCA9 MC_SCLK MCAD1 MCA2 MCAD2 MCA6 MCA3 MCA10 MCA13 MCAD5 EA# RXD REST MCA2 MCA4 MCAD2 MCA0 MCA13 MCAD5 MCAD4 MCAD7 MCA4 MCAD3 MCA0 MCA3 MCA3 MCAD3 MCA11 MCA5 MCA0 MCWR# SCL_analog MCA15 MCAD6 MCAD3 MCA7 TXD MC_DATA MCAD6 MCA14 MCAD7 MCAD4 MCAD2 MCA9 MCA15 MCAD4 MCA7 MCA11 MCA7 MCAD1 PSEN# RST_2300# MCAD0 MCA8 MCA5 MCA9 MCA15 MCAD2 MCA2 MCA6 MCALE MCAD0 RESET RES_2300# RESET# RESET# RESET MC_SCLK 3,4,10 MCALE 10 MCAD[7..0] 10 MC_DATA 3,4,10 MCA8 10 MCA9 10 INTR_ASM# 10 REMOT 3 REST_Analog 3 SDA_analog 3 SCL_analog 3 RES_2300# 4 INTR_analog 3 2596_ON 3,16 JRD# 10 JWR# 10 P3.4 3,4 P1.4 3 MC_SCLK 3,4,10 MC_DATA 3,4,10 X1 8 RESET# 10 GND GND GND GND GND 3.3V GND GND GND GND GND +3.3V_MCU GND +3.3V_MCU +3.3V_MCU +3.3V_MCU +3.3V_MCU +3.3V_MCU +3.3V_MCU GND +3.3V_MCU GND GND +3.3V_MCU GND +3.3V_MCU GND +3.3V_MCU GND +3.3V_MCU GND +3.3V_MCU GND GND +3.3V_MCU GND GND GND +3.3V_MCU GND GND GND 3.3V OR41 100 OR26 OPEN R279 0 C60 0.1uF P8 JST-S5B-PH-K 1 2 3 4 5 +3.3V_MCU RXD TXD EA# GND C450 0.1u OR27 OPEN OR19 OPEN C451 0.1u C198 12pF C452 0.1u OR29 OPEN OR20 OPEN OR17 0 OR30 OPEN U21 SN74LV373A 3 4 7 8 13 14 17 18 1 11 2 5 6 9 12 15 16 19 20 10 D0 D1 D2 D3 D4 D5 D6 D7 OC G Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 VCC GND C213 0.1uF U50 74LV104 4 5 3 2 1 Y VCC GND A NC U24 74LV104 4 5 3 2 1 Y VCC GND A NC C570 100uF/16V Solid Tantalum Y2 27MHZ 1 2 3 OR40 OPEN C553 1u OR10 OPEN Q8 BC847AL 3 1 2 R14_1 0 OR42 OPEN U20A 74lv139 2 3 1 4 5 6 7 16 8 A B G Y0 Y1 Y2 Y3 VCC GND OR15 OPEN U20B 74lv139 14 13 15 12 11 10 9 16 8 A B G Y0 Y1 Y2 Y3 VCC GND U27 DS1819C for 3.3V DS1814C for 5V 4 5 3 2 1 PBRST_ VCC RST GND RST- R206 220 C453 0.1UF OR18 OPEN OR35 OPEN C552 1u U23 SOCKET-DIP32 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 22 24 13 14 15 17 18 19 20 21 16 32 30 1 2 31 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 CE OE DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 GND VCC A17 NC A16 WE OR21 OPEN R9 OR22 OPEN OR28 OPEN OR23 OPEN OR37 OPEN C449 0.1u OR11 4k7 U48 74LV32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1A 1B 1Y 2A 2B 2Y GND 3Y 3B 3A 4Y 4A 4B VCC R267 22 U19 80C251SA/LCC 21 10 43 42 41 40 39 38 37 36 44 22 2 3 4 5 6 7 8 9 24 25 26 27 28 29 30 31 11 13 14 15 16 17 18 19 35 1 23 34 12 20 32 33 X1 RESET P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 VCC GND P1.0/T2 P1.1/T2EX P1.2/ECI P1.3/CEX0 P1.4/CEX1/SS# P1.5/CEX2/MISO P1.6/CEX3/SCL/SCK/WAIT P1.7/CEX4/SDA/MOSI/A17/WCLK P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD/A16 EA/VPP VSS1 VSS2 NMI AWAIT X2 PSEN ALE/PROG SEEPROM U22 AT24C16 1 2 3 4 5 6 7 8 A0 A1 A2 GND SDA SCL TEST VCC OR33 OPEN OR43 OPEN OR34 OPEN R103 47K U31 AM27C020/SO 20 19 18 17 16 15 14 13 3 2 31 1 12 4 5 11 10 6 30 32 7 9 21 22 23 25 26 27 28 29 8 24 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 CE OE PGM VPP D0 D1 D2 D3 D4 D5 D6 D7 VCC GND C199 12pF OR36 OPEN OR16 OPEN R94 4.7K D13 809 3 2 1 VCC RST GND OR38 OPEN C225 1UF 1 2 R93 4.7K OR12 OPEN OR24 OPEN R1 OR25 OPEN R95 open SW1 PB 1 2 3 4 OR39 OPEN D8 809 3 2 1 VCC RST GND C211 0.1uF C215 0.1uF C551 0.01u OR31 OPEN D20 1N5818 R205 4.7k R203 open R280 open OR32 OPEN R204 open C47 1 2 OR14 open R202 open C224 0.1UF 5 4 3 2 1 D D C C B B A A DECOUPLING FOR MISC ICs 2.5V DIGITAL POWER (NEAR uC 80C31 ) (80C32, EPROM, SROM, HC373, HC14, 139, 244, 125) 仅在外销机中安装 00 POWER AND DECAP Custom 16 17 Wednesday, January 26, 2005 Title Size Document Number Rev Date: Sheet of jit_12 jit_12 pannel_12V rela_12 jit_12 2596_ON 3,15 jit_12 jit_12 2596_ON 3,15 2.5V GND 3.3V GND GND GND 3.3V GND GND GND GND +3.3V_MCU +5V +5V +12V GND GND GND INV-12V GND GND GND GND +5V GND pannle_12V GND GND pannle_12V +12V GND GND C569 CAP NP P21 CN2 1 2 FB92 INDUCTOR FB6 1 2 RELA2 Jidian1 1 2 3 4 C566 CAP NP D14 1 2 C567 CAP NP R278 R C574 10uF/16V D15 1 2 D16 1 2 P18 CN2 1 2 R208 100 C564 0.1uF C565 0.1uF U26 RT9172-2.5 1 2 3 4 5 /SD Vin GND Vout FEEDBACK FB54 1 2 C38 10uF/16V FB66 1 2 C208 22uF/16V C447 10uF/35V LM1084CM-3.3 U5 3 2 1 4 IN OUT GND TAB P26 CN2 1 2 12V IN P22 CON4 1 2 3 4 5 LM1117MPX-3.3 U15_1 3 2 1 4 IN OUT GND TAB C40 0.1uF Q9 BC847AL 3 1 2 R265 R CX3 CX R277 R C448 10uF/16V C39 0.1uF R276R C207 22uF/16V Q13 Dianyuan1 G S D CX4 CX C41 47uF/10V FB62 1 2 FB70 1 2 FB85 1 2 C205 47uF/16V FB63 1 2 FB64 1 2 FB84 1 2 FB65 1 2 FB91 INDUCTOR P29 CN2 1 2 FB40 1 2 D9 R288 100 24V IN P19 CON4 1 2 3 4 5 GND GND 24V GND 12V C214 0.1uF C204 0.1uF J1 CN2 1 2 C212 0.1uF RELA1 Jidian1 1 2 3 4 C202 0.1uF R287 R C209 0.1uF C550 22uF/6V C206 22uF/16V C568 CAP NP C203 100uF/10V 5 4 3 2 1 D D C C B B A A Sensitive >=15mil >=15mil Near to 1102 MOS fET and T1 in the same side 1/2 Iout Option_2 5V DIGITAL POWER Option_1 00