5 5 4 4 3 3 2 2 1 1 D D C C B B A A Zoran DVD Player Design---ZR36976 Project: DG0 Version: V40 ZORAN Confidential Abbreviations: 1. NM means "Not Mount". 2. 0R = 0 ohm, 392R= 392 ohms. 3. FB means "ferrite bead". The value of FB such as "220Z" means the resistance =220 ohms @ 100MHz \(including DC and AC). 4. MP means "Mass Production". 5. R&D means "Research & Develop". Notes: 1. Assembly Note (See comments in every schematics page and Implementation/Implementation Option field of each component) 2. The Value of some components shown such as XXX [YYY]. "XXX" is default value, "YYY" is optional value. 3. High current type ferrite bead must be chosen in power supply circuit. 4. Need add "Implementaion" and "Implementation Option" fields when generates BOM. Detail features: 1. Main: ZR36976 + 16/64 Mb SDRAM + 4M/8M/16M serial FLASH ( Default SDRAM is 64M,FLASH is 16M and No EEPROM support) 2. Full OPUs compatibility: DV342 /Mitsumi502W /S71 /KHM313A /HOP1250 /SPU3153 /DPD20428 /Arima (Default: Sanyo HD65) 3. Motor Driver: CD5888 4. Audio: - 6ch DDX - Coax and optical SPDIF output -Microphone input (Internal ADC) 5. Video Output: - CVBS / S-VIDEO / YPrPb(Shared with RGB) 6. Card and USB - USB2.0HS support. - 3 in 1 cards(Default no assemble) 7. HDMI output(Default have CEC function) 8.SCART output(Default no assemble) 8. Debug: - UART 0: shared with FPC_STB and MUTE/HOTPLUG - UART 1: shared with FPC_CLK/CARD_INSERT and FPC_DOUT - ADP ICE: share with UART0 and UART1 These schematics are Zoran confidential and covered by Zoran Non Disclosure Agreement Feature: 　 　 　 　 　 　 　 　 　 　 Version Document 40 DG0 1 8 Wednesday, March 11, 2009 Title Size Document Number Rev Date: Sheet of 5 5 4 4 3 3 2 2 1 1 D D C C B B A A Use it to connect the shell of the crystal with ground. Close to Vaddis! Important power supply! Crystal ZORAN Confidential Close to pin 36 3.30V XXmA EMC usage Atmel: AT26DF081A Note: DDC Capacitance<50pF CEC Capacitance<150pF Pin37--ABCLK Pin38--ALRCLK Pin40--AOUT2 Pin41--AOUT1 Pin42--AOUT0 Pin43--AMCLK These schematics are Zoran confidential and covered by Zoran Non Disclosure Agreement Download Pin1-2 short Power FLASH RESET Pin37--DUPTD1_2 or ICETCK_2 Pin38--DUPRD1_2 or ICETDI_2 Pin41--DUPRD2_2 or ICETDO_2 Pin40--DUPTD2_2 or ICETMS_2 Pin96--HSYNC Pin110--VSYNC Close to Vaddis! Close to Vaddis! NM NM No CEC CEC 0R 27K Function R103 component R104 HDMI output Standby signal L100 C101 3rd overtones crystal 2.7uH 220pF fundamental crystal NM NM Y100 27M 3rd crystal 27M fundamental R124 Fast_Reset 4.7K commonly_Reset NM R126 R125 4.7K 1.3K NM NM Function Q101 BT3904 BT3904 NM NM Q100 The small capacitance close to Vaddis pin ! Close to Vaddis! Close to Vaddis! Type Pin99--SD_D0 Pin100--SD_CLK Pin101--SD_CMD Close to Vaddis! The small capacitance close to Vaddis pin ! R159 2K NM C110 NM 1nF 10nF NM C152 R106 NM 4.7K EC101 NM 10uF/6.3V Download&debug&ICE Pin99 Pin100 UART DUPTD0 DUPRD0 ICE ICETCK ICETMS Pin101 Pin102 DUPTD1 DUPRD1 ICETDI ICETDO Function HOTPLUG: Hi:HDMI output NM BAT54A D102 R142&R138 should be closed to the Vaddis Vaddis_SDRAM_Flash 40 DG0 2 8 Saturday, April 18, 2009 Title Size Document Number Rev Date: Sheet of OSCIN PCLK RAMADD7 RAMCKE PCLK RAMDAT11 RAMCS0- RAMADD0 RAMDAT2 RAMDAT3 RAMDAT10 RAMCAS- RAMADD9 RAMCKE RAMDAT3 RAMDAT13 RAMADD8 RAMADD3 RAMCS0- RAMADD5 RAMADD9 RAMDAT13 RAMADD6 RAMDAT5 RAMDAT9 RAMCKE RAMADD7 RAMDAT14 RAMADD1 RAMDAT12 PCLK RAMDAT0 RAMDAT4 RAMDAT0 RAMDAT1 RAMWE- RAMDQM RAMDAT15 RAMDAT4 RAMADD6 RAMADD2 RAMDAT9 RAMADD10 RAMDAT8 RAMADD10 RAMDAT1 RAMADD11 RAMDAT6 RAMDAT5 SDRAM3.3V RAMRAS- RAMADD4 RAMADD0 RAMCS1- RAMDAT2 RAMDQM RAMADD1 RAMBA RAMADD5 RAMWE- RAMADD3 RAMDAT6 RAMDAT15 RAMDQM RAMDAT11 RAMCAS- RAMADD4 RAMDAT7 RAMDAT12 RAMDAT10 RAMBA RAMRAS- RAMDAT14 RAMDQM RAMDAT7 RAMADD2 RAMDAT8 RAMADD8 SFCLK GP-4 RF_B RF_A RF_E LD_CD SPDL_SENS- LD_DVD RF_F RF_C RF SPDL_SENS+ RF_D SFCLK SFDI SFDO SF_CS SF_CS VDDAFE OSCOUT TMDS_CLK+ TMDS_D0- TMDS_CLK- TMDS_D2+ TMDS_D1+ TMDS_D0+ GP-5 SDRAM3.3V DRVSB Card_enable# OPEN/CLOSE# RAMDAT8 VDDAFE MD_CD RAMADD4 HD_AVDDT33 RAMDAT3 RAMADD3 GP-0 HD_AVDD RAMDAT6 RF_E RF_C RF_B MD_DVD GP-2 VDDPWM RAMDAT9 RAMDAT7 VDDAFE VC DDCDAT0 RAMDAT2 RF_F VDDAFE RAMADD7 VDDDAC FPC_STB HOTPLUG_F# SF_CS RAMDQM RAMCS0- RAMADD10 RFP RAMDAT12 RAMBA RFN RF_A LD_CD TMDS_D2+ SFDI VDDDAC RAMADD9 SPDL_SENS+ SPDL_SENS- VREF DSPVCC18I RAMDAT4 RAMDAT5 RAMADD6 RF_D GP-1 S/PDIF_OUT RAMDAT11 RAMADD0 SLED_PWM FPC_DOUT VFE_YIN RAMDAT13 IPCLK RAMCAS- RAMCS1- RAMRAS- RAMADD8 RAMDAT10 RAMADD11 RAMADD1 GP-3 RAMADD2 LD_DVD VDDPWM RAMADD5 RAMWE- RESOUT FPC_CLK C_B_U Y_R_V DDCCLK0 DDCDAT0 TMDS_D2- TMDS_D0- CEC_1 TMDS_CLK+ DDCCLK0 TMDS_D0+ TMDS_CLK- TMDS_D1+ TMDS_D1- OSCIN OSCOUT VDDPLL RAMDAT0 RAMDAT15 RAMDAT14 RAMDAT1 SDRAM3.3V SLED_PWM SFDO Reset_detect# TRACK_PWM SPDL_PWM FOCUS_S TRACK_S SPDL_S SLED_S SLED_PWM IRRCV DSPVCC33I CVBS_C CVBS_G_Y FLASHVCC33 Power_ON_RESET# HOTPLUG SPDL_SDD0 TRACK_PWM SDD0 SDCLK VDDPLL Reset_detect# Power_ON_RESET# CLK_CARD FPC_CLK FPC_DOUT CLK_CARD FPC_STB DUPTD0 DUPRD0 HOTPLUG_F# HD_AVDDT33 HD_AVDD TMDS_D1- GND CEC_1 Power_ON_RESET# SPDL_PWM SDCMD FOCUS_SDCMD FOCUS_PWM FOCUS_PWM TMDS_D1+ TMDS_D2- S/PDIF_OUT DUPRD0 DUPTD0 APWM_LFE- APWM_LFE- APWM_CEN- RF C_B_U VC MD_DVD MD_CD LD_CD LD_DVD S/PDIF_OUT FPC_CLK APWM_R- APWM_SL- APWM_SR- APWM_L- RF_C RF_A RF_B SPDL_SENS- VFE_YIN RF_D RF_E SPDL_SENS+ RF_F IRRCV DRVSB FPC_STB FPC_DOUT Y_R_V FS1 USB_DP USB_DN FS2 OPEN/CLOSE# SLED_S SPDL_S TRACK_S FOCUS_S CVBS_C CVBS_G_Y Card_enable# SDCLK SDD0 HOMESW# FS-2 SDCMD LED_R1 SDRAM3.3V VDDAPWM DSPVCC33I DSPVCC33I DSPVCC33 HDMI5V TDMSGND TDMSGND DSPVCC18I DSPVCC33 DSPVCC33 FLASHVCC33 DSPVCC33 HDMI5V DSPVCC33I DSPVCC18 DSPVCC33 DSPVCC18 DSPVCC18I DSPVCC33 DSPVCC33I DSPVCC33I DSPVCC33I C154 10nF C122 10nF C102 22pF C159 1nF C116 1nF U104 [16Mbit: K4S161622C-TC/L70] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VDD DQ0 DQ1 VSSQ DQ2 DQ3 VDDQ DQ4 DQ5 VSSQ DQ6 DQ7 VDDQ LDQM WE CAS RAS CS BA A10/AP A0 A1 A2 A3 VDD VSS DQ15 DQ14 VSSQ DQ13 DQ12 VDDQ DQ11 DQ10 VSSQ DQ9 DQ8 VDDQ NC UDQM CLK CKE NC A9 A8 A7 A6 A5 A4 VSS C144 33pF + EC103 220uF/16V R101 1.5K Ohm 1% C143 1nF R128 1K R119 150R Q103 [BT3904] 1 2 3 C909 1nF FB106 MBW2012-221 C152 [10nF] + EC105 220uF/16V C106 10nF R130 4.7K C158 1nF Q100 [BT3904] 1 2 3 C163 1nF C149 1nF R129 4.7K R132 33R C131 10nF R122 NC R108 1.8K R149 10K Y100 27.000MHz fundamental [27.000M 3rd overtones] R138 1K + EC111 220uF/16V C105 10nF U100 SPI FLASH-SOP8 1 2 3 4 5 6 7 8 /CS SO /WP GND SI SCK /HOLD VDD TP115 1 . C132 NC C121 10nF C160 27nF C107 10nF R102 15.4K 1% C108 10nF R110 33R R152 10R C118 10nF R146 51K R142 10K C138 NC C136 NC R104 27K R124 [4.7K] + EC110 220uF/16V C135 NC R126 [1.3K] C150 1nF L905 10UH R141 [100R] C117 10nF L100 2.7uH(nc) FB101 MBW2012-221 C155 10nF L998 FB/0402 + EC102 220uF/16V R155 10K R144 1K C109 10nF C142 1nF R117 150R R151 4.7K C120 10nF R118 150R C157 10nF + EC104 NC C111 0.1uF C104 10nF R107 75R L999 FB/0402 R137 10K C137 NC R120 56R C110 1nF(NC) C164 100pF + EC107 220uF/16V FB107 MBW2012-221 C112 1nF R125 [4.7K] FB102 MBW2012-221 C119 10nF R127 1K R105 220K FB108 MBW2012-221 C153 10nF + EC100 220uF/16V FB103 MBW2012-221 R123 220R R159 [2K] D102 4148 1 2 + EC106 220uF/16V FB109 MBW2012-221 R154 [6.8K] C146 NC U101A ZR36976 94 93 55 56 49 101 86 84 87 85 83 82 88 90 72 81 74 78 79 76 77 73 70 71 75 69 68 95 105 103 106 107 115 108 125 124 126 127 128 1 2 3 4 5 7 6 8 10 9 11 13 14 15 16 12 17 18 20 19 21 23 22 24 25 27 26 28 29 31 34 32 33 35 92 91 67 66 65 62 61 112 111 63 114 113 110 59 98 96 57 44 43 42 41 40 38 118 121 122 123 30 36 37 109 104 46 47 48 117 116 89 80 99 50 54 53 64 52 51 58 119 120 100 39 97 45 60 102 SPINDLE_PWM/SD_DO TRACK_PWM/SD_CLK/GPIO[50] TXD2N TXD2P TXCN SD_CMD/IGPIO[11]/DUPTD1 DVD_MD VDDSAFE CD_LD CD_MD RESLOAD VREF DVD_LD FOCUS_PWM/SD_CMD/GPIO[49] B VC C K F J E VDDAFE VDDAFE A D RFIN_N RFIN_P SLED_PWM/GPIO[52] SFCS GNDC SFDO SFDI VDDC VDDP RAMADD[6] RAMADD[2] RAMADD[1] RAMADD[7] GNDC RAMADD[0] VDDP RAMADD[8] RAMADD[10] RAMADD[9] RAMCS0# RAMADD[11]/GPO[64] RAMBA RAMRAS# RAMCS1#/GPO[65] RAMCAS# RAMDQM GND_PCLK PCLK VDD_PCLK RAMWE# RAMDAT[8] RAMDAT[7] RAMDAT[6] RAMDAT[9] RAMDAT[10] RAMDAT[11] RAMDAT[5] RAMDAT[4] RAMDAT[12] VDDP RAMDAT[3] RAMDAT[13] RAMDAT[2] RAMDAT[1] VDDC RAMDAT[15] RAMDAT[0] GND_APWM VDDC VDDPWM RSET DAC1 DAC2 VDDDAC DAC4 XI XO DAC3 VDDPLL GNDPLL RESET#/GPO[15]/VSYNC VDDC_HDMI IGPIO[37] PWMCO[5]/IGPIO[55]/HSYNC VDDP_HDMI SFDIF_O2/GPIO[20] APWM[0]/AMCLK APWM[1]/AOUT[0] APWM[2]/AOUT[1]/GPIO[26] APWM[3]/AIN/GPIO[25] APWM[4]/ALRCK/GPIO[24] USB_DN RAMADD[4] RAMADD[3] RAMADD[5] RAMDAT[14] VDD_APWM APWM5/ABCLK/IGPIO[23] SFCLK SD_DO/GPIO[34] DDCDAT DDCCLK CEC USB_DP USBVDD VFE_YIN GND1AFE PWMCO[2]/GPIO[47]/DUPTD0 TXCP TXD1P TXD1N GNDC TXD0P TXD0N TXREXT USBREF USBVDDPLL1P8 PWMCO[1]/IGPIO[7]/DUPRD0 GNDC SD_CLK/GIPO[39] VDDP VDDC PWMCO[4]/GPIO[27]/DUPRD1 C130 10nF C140 NC C156 10nF C115 0.1uF R157 10K Q101 [BT3904] 1 2 3 C141 NC R106 4.7K(NC) R111 33R C113 0.1uF C128 10nF R115 392 Ohm/1% U103 64Mbit:K4S641632H-UC70 [NM] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD DQML WE# CAS# RAS# CS# BA0 BA1 A10 A0 A1 A2 A3 VDD VSS A4 A5 A6 A7 A8 A9 A11 NC CKE CLK DQMH NC VSS DQ8 VDDQ DQ9 DQ10 VSSQ DQ11 DQ12 VDDQ DQ13 DQ14 VSSQ DQ15 VSS FB104 MBW2012-221 R143 [100R] C103 22pF C161 27nF J100 HD port 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 TDMS_D2+ TDMS_D2_SHIELD TDMS_D2- TDMS_D1+ TDMS_D1_SHIELD TDMS_D1- TDMS_D0+ TDMS_D0_SHIELD TDMS_D0- TDMS_CLK+ TDMS_CLK_SHIELD TDMS_CLK- CEC NC SCL SDA DDC/CEC_GND +5V HOTPLUG GND GND GND GND C100 0.1uF C134 NC R100 10K C162 100pF C147 0.1uF + EC101 10uF/16V(NC) C133 NC C139 NC FB100 MBW2012-221 R147 22K C151 10nF C114 1nF C129 10nF + EC108 220uF/16V R109 1.8K + EC109 220uF/16V R121 6.19K 1% C145 10nF FB105 MBW2012-221 C101 220pF(nc) C127 10nF R148 51K TP113 1 . R156 [100R] CON13 DOWN_LOAD_I/F key 1 2 3 4 JP101 2Pin*2.0 1 2 1 2 R116 150R R145 51K FB111 MBW2012-221 R158 51K(NC) 5 5 4 4 3 3 2 2 1 1 D D C C B B A A 3 C CN201 is used for Sanyo/Samsung/Sony OPUs 2.1V 1 B 2 E S8050/S8550 Q210, 211 must have enough large pads for thermal spreading ZORAN Confidential 1.18V 1.18V BEMF Current Type(Default) R202=300R, for HOP1200W only In servo 3.3V power supply circuit: R214,EC203,C217,R217,EC204 need to be closed up when do layout PDIC Control: DVD=LOW CD=HIGH These schematics are Zoran confidential and covered by Zoran Non Disclosure Agreement Main Power R233 close to Q202 R231 close to Q201 OPEN&CLOSE&IN_SW&OUT_SW circuit MITSM820W HD65/HD62 NM 0 IAT510 502W 0 100R 91R TOP1100S R208 Arima681 91R 10R 0 0 SEMCO-SP1 NM HD8(DV23) 0 NM R207 OPU Sony310 100R 91R 91R HOP1200W 0 10R DL3 NM 100R 0 100R 0 Other R237 R230 OPU HOP1200W NM Arima681 100R 100R NM 100R 100R 18K 1% 2K 1% R212 R211 Motor driver CD5888(1.18V) AM5888 10K 1% 1.2K 1% R213 11K 1% 430R 1% 3.3R 3.3R HD65PS OPU R214 R217 Other 4.7R 4.7R The package should be 0603 R223 20K 1% 1K 1% 4.7R HD850 4.7R NEC Toshiba 8.2R 8.2R FE_Regulator 40 DG0 3 8 Wednesday, March 11, 2009 Title Size Document Number Rev Date: Sheet of 3V3_DRV 3V3_FB 1V8_DRV 1V8_FB VC1 VR_CD VR_DVD TACT+ TACT- FACT+ FACT- DVDLD CDLD OPU_HFM OPU5V SPDL_SENS+ LOAD- LOAD+ IN_SW# HOMESW# SPDL_SENS- SP_M- SP_MOT- VR_CD VR_DVD TACT- SP_MOT+ TRACK_S TACT+ FOCUS_S 1V8_FB 3V3_DRV 1V8_DRV SL_MOT+ SL_MOT- LOAD+ SPDL_S CLOSE FACT- OPEN FACT+ LOAD- 3V3_FB VC2 SLED_S SP_M- SP_MOT- DVDLD CDLD CD_DVD OPEN IN_SW# OUT_SW# OPEN/CLOSE# CLOSE OUT_SW# SL_MOT- SP_MOT+ SL_MOT+ RF_A RF_B RF_C RF_D RF RF_F RF_E LD_DVD LD_CD VC MD_CD MD_DVD HOMESW# SPDL_SENS+ SPDL_SENS- DRVSB OPEN/CLOSE# TRACK_S SPDL_S SLED_S FOCUS_S RFA5V DSPVCC33 DSPVCC33 M5V RFA5V DSPVCC33 DSPVCC33 M5V M5V DSPVCC33 DSPVCC33 DSPVCC33 DSPVCC18 DSPVCC33 C203 NC + EC204 220uF/16V Q202 BT2907 1 2 3 R212 18K 1% R234 33K TP15 C223 0.1uF C216 0.1uF R230 91R(NC) TP5 + EC200 220uF/16V CON5 5x1 W/HOUSING 5 4 3 2 1 TP16 D201 BAT54C 2 3 1 R228 1K 1% R217 8.2R R204 10K R231 10K C204 0.1uF C213 NC TP17 C207 1nF C222 1nF D202 1N4001 1 2 R233 NC TP6 C215 NC TP18 + EC207 220uF/16V R205 10K TP7 + EC201 220uF/16V R207 0R Q204 SS8550 Fairchild 2 1 3 Q205 BT3904 1 2 3 R202 0R TP19 C220 1nF R223 22K 1% R216 220R Q201 BT2907 1 2 3 TP8 + EC205 220uF/16V R215 220R C202 0.1uF R206 1K R232 47K R235 2.2R TP1 + EC206 220uF/16V R236 2.2R C219 220pF C208 100P U200 CD5888CB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 29 30 VINFC CFCERR1(TRB_1) CFCERR2(REGO2) VINSL+ VINSL-(REGO1) VOSL(FWD) VNFFC(REV) VCC PVCC1(LOAD-) PGND(LOAD+) VOSL-(VOSL+) VOSL+(VOSL-) VOFC- VOFC+ STBY BIAS VINTK CTKERR1(TRB_2) CTKERR2(NC) VINLD PREGND PVCC2 VNFTK(NC) PGND(VCC2) VOLD- VOLD+ VOTK- VOTK+ GND GND1 TP9 C201 0.1uF R214 8.2R C224 0.1uF + EC203 220uF/16V C212 NC TP10 R229 1K 1% Q203 SS8550 Fairchild 2 1 3 C205 1nF L200 10uH TP2 C206 1nF C209 NC TP11 D200 1N4001 1 2 R222 47K CON2 6x1 W/HOUSING 1 2 3 4 5 6 TP3 R208 0R R218 NC R209 1K C211 NC R210 33R R211 11K 1% TP12 R239 2K C221 220pF R203 3.3K C217 0.1uF TP4 CN200 24Pin OPU connector 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 25 26 27 28 GND-LD DVD-LD NC HFM MD CD-LD VR-DVD VR-CD NC E VCC VC(VREF) GND/PD F B A RF CD/DVD_SW D C T- T+ F+ F- GND GND GND GND Q200 BT3906 1 2 3 TP13 + EC202 47uF/16V R213 10K 1% R237 91R(NC) C218 100P R226 2K R227 4.7K C210 0.1uF C214 NC TP14 5 5 4 4 3 3 2 2 1 1 D D C C B B A A ZORAN Confidential These schematics are Zoran confidential and covered by Zoran Non Disclosure Agreement Digital audio output Analog audio output BT3904 56R NM No cost down cost down NM NM 150R R363 Type Q310 Parts R360 R364 62R 27R R361 39R 82R OP+ OP- OP- OP- OP+ OP- OP+ OP+ OP- OP+ OP+ OP- MIC Mute Circuit Audio_Input_Output 40 DG0 4 8 Tuesday, April 28, 2009 Title Size Document Number Rev Date: Sheet of OPTICAL_SPDIF S/PDIF_OUT COAX_SPDIF GND CEN-OUT LMAIN-OUT RMAIN-OUT SR-OUT LFE-OUT SL-OUT OPTICAL_SPDIF LFE-OUT MUTE_2 MIC_L MUTE_2 CEN-OUT MIC_R SR-OUT MUTE_2 SL-OUT MUTE_2 MUTE_2 MUTE_2 GND MIC_R MUT MIC_L VFE_YIN +12VA MUTE1 MUTE_2 MUTE_CTL S/PDIF_OUT COAX_SPDIF RMAIN-OUT LMAIN-OUT VFE_YIN FPC_DOUT APWM_R- APWM_SL- APWM_SR- APWM_CEN- APWM_LFE- APWM_L- D5V D5V +12V P-12V P-12V +12V +12V P-12V +12V P-12V P-12V +12V +12V P-12V VCC P+12V P-12V D5V +12V R300 6.2K 1% R358 47K + C397 4.7uF/50V R303 51K C371 1.2nF R366 100K RK2 10k(NC) Q310 BT3904(NC) 1 2 3 CON7 SPDIF 3 1 2 8 4 5 6 7 + EC314 4.7uF/50V C392 62pF R375 470R R334 470R + CK2 10uF/16v(NC) + EC305 47uF/16V R317 1K C362 75pF + C398 4.7uF/50V R302 4.7K R365 62R R360 56R(NC) R321 470R 27pF C905 C303 1uF C319 22pF RK1 10k(NC) + EC317 4.7uF/50V + CK1 10uF/16v(NC) R370 39K R345 470R R323 82K R396 1K R333 4.7K R331 10K R301 10K + C399 4.7uF/50V 27pF C913 + - U305A LM4558 3 2 1 8 4 R373 4.7K C351 1.2nF R304 100R R350 39K R332 82K + - U304B LM4558 5 6 7 8 4 Q801 8550 1 2 3 C322 0.1uF R344 1K Q802 8050 1 2 3 R327 10K R363 [150R] + C340 4.7uF/50V D300 LL4148 1 2 R343 4.7K R8031k R394 39K + EC318 4.7uF/50V R801 4.7k C352 75pF CON9 7P2.0 [NM] 1 2 3 4 5 6 7 C320 0.1uF + - U301A LM4558 3 2 1 8 4 Q300 BT3904 1 2 3 R316 1K + C349 4.7uF/50V 27pF C911 R362 82K C391 2nF Q302 8550 1 2 3 R319 470R R325 10K C372 75pF C361 1.2nF R324 4.7K R361 [82R] 27pF C906 R340 39K Q301 BT3904 1 2 3 + EC319 4.7uF/50V R372 82K C332 62pF EC300 220uF/16V R329 10K R352 82K + EC316 4.7uF/50V R364 62R [27R] R355 10K + - U304A LM4558 3 2 1 8 4 Q902 8050 1 2 3 R305 1.1K 1% + EC301 4.7uF/16V Q903 8050 1 2 3 FB300 MBW2012-221 + - U301B LM4558 5 6 7 8 4 27pF C914 R320 39K Q904 8050 1 2 3 + EC320 4.7uF/50V C321 2nF Q905 8050 1 2 3 R307 4.7K R330 39K R805 0R Q906 8050 1 2 3 C341 1.2nF Q901 8050 1 2 3 R374 1K R353 4.7K C801 4.7UF + EC312 47uF/16V R308 1K C342 75pF R804 4.7k R354 1K R391 4.7K 27pF C912 R328 10K + C396 4.7uF/50V R802 1k CN406 Audio out [NM] 1 2 3 4 5 6 7 R393 470R + - U305B LM4558 5 6 7 8 4 R342 82K 5 5 4 4 3 3 2 2 1 1 D D C C B B A A ZORAN Confidential These schematics are Zoran confidential and covered by Zoran Non Disclosure Agreement At middle of trace. 0---2V 4.5---7V 9.5---12V 1---3V 0---2V 1---3V 1---3V 0---0.4V RGB CVBS 16:9 4:3 4:3 TV 0---0.4V 0---0.4V state TV Mode RGB Staus 16:9 4.5---7V Video Stause 9.5---12V Video Status RGB Status SCART config circuit HDMI 5V power 6.8K R413 Q402 NM 1 PWM control SCART NM R154 6.8K Common SCART Parts R411 150R BT3904 R412 1.5K 100R 1.8K 330R 3 in 1 cards (MMC\SD\MS) VFD drive signal Note:HDMI5V voltage spec :4.8V__5.2V NM 22R/0805 1K 0R BZT52C5V6S NM NM NM Q400 R401 D400 NM STBY5V R403 parts 4.8V--5.2V R400 S8050 <4.8V&>5.2V EC400 NM 10uF/6.3V R432 R141 4.7K R426 R143 51K R430 3in1 card R156 BT3904 100R R431 2N7002 Q102 100R Save 1 GPOI Parts CN405 NM 100R Q403 10K C432 7Pin*2.0 10nF R415 BAT54S C436 10K Q404 0.1uF NM NM NM NM C435 NM D406 220pF KTC3875 R416 NM 100R R434 100K 10K R433 NM NM 4.7K 51K BT3904 100R 2N7002 100R 1K 100R 10K 7Pin*2.0 10nF NM R427 NM no MS card 0R NM NM NM 1K 100R NM 100R NM NM 10nF 7Pin*2.1 NM 100R R417 1.8K 1.5K Q401 BT3904 BT3904 1uF C433 1uF 0R 0R R327 0R 0R R328 R157 10K NM CN401 11Pin*2.0 11Pin*2.0 R414 NM NM R425 1K 1K Analog video output Power input +12V: +12V(+-10%) +5V: +5V(+-2.5%) POWER USB 500mA for device DG0 5 8 Wednesday, April 29, 2009 40 Power_Video _USB_3in1 cards Title Size Document Number Rev Date: Sheet of RGB/CVBS# TV/16:9/4:3 SD_CMD SDCMD FPC_CLK HDMI5V SD_SCLK SDCLK /CARD_INSERT# SDD0 SD_D0 RMAIN-OUT CVBS_OUT LMAIN-OUT COAX_SPDIF G-Y_OUT C-B-U_OUT Y-R-V_OUT Y-R-V_OUT C-B-U_OUT P+5V P+12V STBY5V P+12V CLK IR DAT LED_R IRVCC STB RGB/CVBS# CVBS_OUT G-Y_OUT TV/16:9/4:3 C-B-U_OUT Y-R-V_OUT RMAIN-OUT GND LMAIN-OUT GND DSPVCC33 SD_SCLK SD_CMD /CARD_INSERT# SD_D0 C-B-U_OUT Y-R-V_OUT C_B_U CVBS_G_Y G-Y_OUT CVBS_C CVBS_OUT Y_R_V USB_DN USB_DN1 USB_DP1 USB_DP STB CLK DAT P+5V IRVCC IR FPC_CLK ctrl ctr2 ctrl LED_R1 ctr2 LED_G LED_G LED_R FS2 Card_enable# SDD0 SDCMD SDCLK FS1 LMAIN-OUT COAX_SPDIF RMAIN-OUT RMAIN-OUT LMAIN-OUT CVBS_C CVBS_G_Y C_B_U Y_R_V USB_DN USB_DP IRRCV FPC_CLK FPC_DOUT FPC_STB FS-2 LED_R1 D5V +12V HDMI5V D5V DSPVCC33 D5V RFA5V +12V M5V STB5V GND P+12V P-12V GND P-12V P-12V GND GND M5V M5V M5V M5V D5V GND GND P+12V P+12V STB5V STBY5V M5V D5V D5V R417 [1K] C433 [1uF] R703 10k R410 2.2K C496 NC R411 [1K] + EC400 [10uF/16V] R901 75 L401 0R/0603 G G C Y CON10 S-VIDEO + RCA 2 1 6 3 7 9 4 5 8 0.1uF BC9 L904 FB R177 27R R408 10K R905 0/NC C429 NC MARK1 1 . C411 NC L22 FB CN405 SD card [NM] 1 2 3 4 5 6 7 R414 [1K] L16 FB D403 BAV99 C421 100P 0.1uF BC10 CON4 8x2.0 W/HOUSING HEADER8-2.0 8 7 6 5 4 3 2 1 C424 NC C434 10nF D404 BAV99 CON1 P4/2.54 1 2 3 4 R706 0R(nc) C425 10nF Q911 2N3906 1 2 3 C423 150pF R413 [150R] L17 FB Q912 2N3906 1 2 3 R409 10K 33pF C65 CON11 10/2.0 W/HOUSING HEADER10-2.0 1 2 3 4 5 6 7 8 9 10 H4 H4 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 C413 NC R902 75 R426 [1K] 27pF C902 0.1uF BC8 C491 150pF L18 FB FB409 MBW2012-221 L901 FB R702 [470R] CON8 AUDIO&VIDEO-OUT 9 8 7 6 5 4 3 2 1 C418 NC EC23 220uF/16V H3 H3 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 D401 BAV99 R424 33R L403 0R/0603 C419 100P D402 BAV99 MARK2 1 . R490 0R L404 0R/0603 R412 [100R] Q701 [BT3904] 1 2 3 Q102 [BT3904] 1 2 3 C427 10nF EC24 220uF/16V C178 56pF R430 [10K] C420 100P L902 FB 33pF C64 C180 56pF R701 10k 27pF C904 C490 NC Q401 [BT3904] 1 2 3 C415 NC R705 0R(nc) R423 33R C432 [10nF] C492 NC R903 75 Q914 2N3906 1 2 3 R407 10K R906 0/NC Q402 [BT3904] 1 2 3 C494 150pF FB901 MBW2012-221 C493 150pF CON12 4x1 W/HOUSING 1 2 3 4 + EC401 220uF/16V R431 [4.7K] R904 75 FB406 FB C417 100P C426 10nF Q913 2N3906 1 2 3 R179 15K 0.1uF BC5 L15 FB 27pF C901 C430 NC C422 100P R418 33R C414 NC L903 FB R427 NC Q702 [BT3904] 1 2 3 R432 [51K] C428 10nF R907 0/NC L402 0R/0603 0.1uF BC4 R422 33R R176 27R R178 15K 0.1uF BC11 27pF C903 C431 NC Q403 [2N7002] 1 3 2 R704 [470R] R908 0/NC 5 5 4 4 3 3 2 2 1 1 D D C C B B A A OPTIC COAXIAL S-VIDEO OUT R L LFE CEN U Y V CVBS ZORAN DG0_V40 SR SL CVBS HDMI These schematics are Zoran confidential and covered by Zoran Non Disclosure Agreement DG0 6 8 Wednesday, March 11, 2009 40 Back panel Title Size Document Number Rev Date: Sheet of 5 5 4 4 3 3 2 2 1 1 D D C C B B A A These schematics are Zoran confidential and covered by Zoran Non Disclosure Agreement V20 VS V10 1.Change net “HOMESW#” from pin107 of 976 to pin106 of 976.(20080530) 2.Change net “Reset_detect#” from pin106 of 976 to pin107 of 976(20080530) 3.Change R128 value from 6.8K to 1K(20080612) 4.Change R144 value from 6.8K to 1K.(20080612) 5.Remove R428 Q404 R429 Q405 C148 and add R432 (20080614) 6.Change R126 value from 1.5K to 1.3K(20080614) 7.Change R127 value from 1.5K to 1K (20080614) 8.Change R151value from 1K to 4.7K(20080614) 9.Add R159 C152(20080614) 10.Change R142 value from 10K to 5.1K 20080530 （ ） 11.Change R400 value from 22R/0805 to NM(20080614) 12.Change R401 value from 1K to NM(20080614) 13.Change Q400 value from S8050 to NM(20080614) 14.Change D400 value from BZT52C5V6S to NM(20080614) 15.Change R402 value from 4.7K to NM(20080614) 16.Change EC400 value from 10uF/6.3V to NM(20080614) 17.Add R403 and C434(20080614) 18.Remove D102 and D103(20080614) 19.Change R141 R143 R156 value from 33R 100R(20080614) 20.Remove R201 and add D202 (20080614) 21.Change R222 value from 4.7K to 47K(200806014) 22.Remove R200 R220 C200 R221(20080614) 23.Change R204 value from 1K to 10K(20080614) 24.Change R206 value from 10K to 1K(20080614) 25.Change Q200 value from BT3904 to BT3906(20080614) 26.Remove R218 R219(20080614) 27.Remove R131 R133 R134 R135(20080614) 28.Remove FB402 FB403 FB404 FB405 EC404 R415 R416(20080614) 29.Remove R404 C402 R406 C401 R152 R153(20080614) 30.Add D102 R131 R160 D202(20080617) 31.Remove R142 R138 Q103(20080617) 32.Change R155 from value from 4.7K to 1.5K(20080617) 33.Change R201 value from 4.7R/1W to 3.3R/1W.(20080617) 34.Change R306 value from 10K to 10K.(20080617) 35.Change R303 value from 6.8K to 13K.(20080617) 36.Change R304 value from 220R to 100R(20080619) 37.Change EC301 value from 10uF/16V to 4.7uF/16V(20080619) 38.Change R308 value from 4.7K to 10K(20080619) 39.Change R315 R313 R333 R326 R345 R350 value from 1K to 2K(20080619) 40.Exchange Q308 Q309 Q304 Q305 Q306 Q307 pin2 and pin3 net.(20080619) 41.Add R218(20080619) 42.Change R123 value from 100R to 220R.(20080623) 43.change EC100 value from 680uF/6.3V to 220uF/6.3V.(20080623) V20_T1 VS V20 1.change R155 value from 1.5K to 10K(20080813) 2.Remove R160 and add R142 R138(20080813) 3.Change R303 value from 13K to 18K(20080813) 4.Change R305 value from 1.3K to 1.1K(20080813) 5.Change R308 value from 10K to 1K.(20080813) 6.Change R306 value from 20K to 47K.(20080813) 7.Change R301 value from 4.7K to 10K(20080813) 8.Remove D102 R131 (20080818) 9.Add R152 R153 U102 D102(20080818) V40 VS V30 1.Change the net of HOTPLUG_F# from P100 to Pin99 2.Change the connection of R156 from Pin93 to Pin100, and name CLK_CARD. 3. Change the net alias of Pin100 of V976 from HOTPLUG_F# to CLK_CARD. 4.Change the value of C330 from NM to 33pF 5.Change the value of D302 from NM to BAT54S 6.Change the value of C331 from NM to 10nF 7.Change the value of R359 from NM to 15K 8.Change the value of R362 from NM to 3.3K 9.Change the value of R303 from 18K to 6.8K 10.Disconnect the control circuit from SDCLK, and directly connect SDCLK to Pin2 of CN405. Then add the control circuit between SDD0 and Pin6 of CN405. (The control circuit include some components of R427,Q403,R432,R430,R431,Q102) 11.Change the value of R115 from 430R 1% to 392R 1% 12.Romove R152 R153 U102 R306 13.Change the PCB footprint FB105 from 0805 to 0603 14.Change the value of R213 from 510 1% to 1.1K 1% 15.Change the value of R223 from 1K 1% to 2K 1% 16.Change the value of R201 from 3.3R to NM 17.Change the value of D202 from NM to IN4001 18.Remove EC403 D405 R420 R421 R339 EC321 19.Change the value R419 form 1K to 10K. 20.Add C407 C332R134 R133 R131 Q1 C123 C165 TP117 C162 EC402 FB109 R152 C164 C163 21.Change the value of R376 from 10K to 100K 22.Change the value of R357 from 100K to 1M 23.Change the value of EC305 from 220uF/16V to 47uF/16V 24.Change the value of R212 from 1.8K to 18K 25.Change the value of R211 from 1K to 10K DG0 7 8 Wednesday, March 11, 2009 40 ECO Title Size Document Number Rev Date: Sheet of 5 5 4 4 3 3 2 2 1 1 D D C C B B A A (1)调整TMDS 布线 1)所有TMDS走线长度严格控制在18mm 以内； 2)所有TMDS走线不能有过孔且需要在同一层； 3)所有TMDS走线拐弯处禁止走45度或90度角； 4)所有TMDS走线需要保持相同的宽度； 5)差分对正负信号(CLK+和CLK-；D0+和 D0-；D1+和D1-；D2+和D2-)走线必须平行且之间的间距相等。 TMDS 下面给出 走线的例子 (2)TMDS走线区域有以下规定 1) TMDS ; ; ; 以下 走线层区域禁止走地线和电源线 禁止走任何信号线 禁止铺铜 禁止铺阻焊绿油： a)差分对与差分对之间的区域； b)位于CLK-信号线下面且距离此线大于或等于30mils的空间； c)位于D2+信号线上面且距离此线大于或等于30mils的空间； d)差分对正负信号(CLK+与CLK- ; D0+与D0-;D1+与D1-;D2+与D2-)之间的区域。 , 下面是基于此规则给出的例子 图中各区域分别表示： 1--差分对正负信号之间的区域； 2--D2+ 30mils 上面 的区域； 3--差分对与差分对之间的间距； 4--CLK- 30mils 下面 的区域。 (3)TMDS 走线阻抗严格控制在146 ohm +/-10%以内 1)板材的厚度必须大于或等于1mm； 2)差分对与差分对之间的间距大于或等于30mils； 3)差分对正负信号之间的间距为8mils； 4)TMDS 走线宽度为5mils； 5)铜箔厚度为1oz； 6)距离HDMI座子30mil的所有TMDS走线必须与座子对应脚平行。 下面给出例子 1 Adjust the differential traces as follows: 1-1 The length of all TMDS traces must be controlled within 18mm; 1-2 All TMDS traces must be at the same layer and forbid any via on the trace; 1-3 All TMDS traces must not be 45 degree angle or 90 degree angle; 1-4 The width of all TMDS traces must be the same; 1-5 The positive and the negative traces of each differential pair (CLK+ and CLK-, D0+ and D0-, D1+ and D1-, D2+ and D2-) must be parallel, and the clearance between them must be the same. The follow figure is the example of TMDS layout: 2 On the area of TMDS traces, must do as follows: 2-1 On the layer of TMDS traces, there must be no GND trace, no power trace, no other signals trace, no flooding with copper, no solder mask (green oil paint) on the area as follows: 2-1-1 The space between the neighboring differential pairs (CLK vs. D0, D0 vs. D1, D1 vs. D2); 2-1-2 The space under the trace CLK- with the distance from this trace about or more than 30mils; 2-1-3 The space above the trace D2+ with the distance from this trace about or more than 30mils; 2-1-4 The space between the positive and the negative traces of each differential pair (CLK+ and CLK-, D0+ and D0-, D1+ and D1-, D2+ and D2-). The follow figure is the example based on these rules, and each number in the figure means: 1--The space between the positive and the negative traces of each differential pair 2--The space above the trace D2+ with the distance from this trace 30mils; 3--The space between the neighboring differential pairs; 4--The space under the trace CLK- with the distance from this trace 30mils. 3 The impedance of TMDS traces must be controlled as 146 ohm +/-10% strictly 3-1 The thickness of PCB board is 1mm or more than 1mm; 3-2 The clearance between the neighboring differential pairs is 30mils or more than 30 mils; 3-3 The clearance between the positive and the negative trace of each differential pair is 8mils (S1=8mils); 3-4 The width of TMDS trace is 5mils (W1=5mils); 3-5 The thickness of the copper coil on PCB board is 1oz (T1=1.8mils); 3-6 All the TMDS traces must be adjusted to be parallel with the corresponding pin of the connector when there is 30mils distance from HDMI connector. The follow figure is the example: TMDS layout rule(based on the two-layer board of FR4) TMDS ( FR4 ) 布板规则 基于 双层板 (4) HDMI PCB , PCB HDMI 任何 方案设计的 加工时 都必须要求 加工厂对空板上 差分线进行阻抗测试 4 Any PCB board manufacture for HDMI solution, must ask the factory to do impedance measure for HDMI differential traces on the empty board. 2)TMDS , ; 走线层背面区域尽量保证一个完整的地平面 禁止走电源线 禁止走任何信号线。 下面是基于此规则给出的例子： 2-2 On the opposite layer of TMDS traces, there must be a whole GND plane and no power and no other signals trace. The follow is the example based on this rule: These schematics are Zoran confidential and covered by Zoran Non Disclosure Agreement DG0 8 8 Wednesday, March 11, 2009 40 HDMI TMDS layout rule Title Size Document Number Rev Date: Sheet of